diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-04-19 21:43:52 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-04-21 13:26:57 -0700 |
| commit | 0de8eb33344ed2d4b36d3c82babdef6cd1ff1fb2 (patch) | |
| tree | 37d5173b8057bfc34d7c0e03dbbd3a1ca0af2d21 /drivers | |
| parent | 35367088ddab9684ea29432ce35d2a3f117a9d6b (diff) | |
tegra RM: Upadted CPU clock control in LP2 state.
Upadted CPU clock control in LP2 state:
- Disabled PLLX on entry to LP2
- Forced CPU divider 1:1 setting on entry to LP2, and restore divider
on exit (speed up LP2 entry/exit)
- Removed PLLC and PLLM from wake source consideration (commonly these
PLLs are disabled in LP2 anyway, but using them in rare case when they
are available may create dangerous over-clocking condition)
Change-Id: Ied51ebee553766e66d6007e1149270e243df0543
Reviewed-on: http://git-master/r/1155
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'drivers')
0 files changed, 0 insertions, 0 deletions