diff options
| author | Kevin Huang <kevinh@nvidia.com> | 2013-01-29 15:12:52 -0800 |
|---|---|---|
| committer | Harshada Kale <hkale@nvidia.com> | 2013-10-07 00:06:40 -0700 |
| commit | ae306268afc1c478740096f4d89875db90b03b6d (patch) | |
| tree | 1a8ee80a0dd34fde8ed4e42039863804ef65d7e3 /drivers | |
| parent | 4da602d0f09949085b67a42341268dcb004f22e7 (diff) | |
video: tegra: dc: WAR of SHIFT_CLK_DIV update.
Bug 1225291
Bug 1161019
Bug 1363029
Change-Id: I699e64a1f6464eeddae5275a55cd2b285badc698
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/195272
Reviewed-on: http://git-master/r/281537
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Tested-by: Rakesh Iyer <riyer@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/video/tegra/dc/dsi.c | 17 | ||||
| -rw-r--r-- | drivers/video/tegra/dc/mode.c | 17 |
2 files changed, 33 insertions, 1 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index fdfe87e90eee..848bbadca948 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/dsi.c * - * Copyright (c) 2011-2012, NVIDIA CORPORATION, All rights reserved. + * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -1752,9 +1752,24 @@ static void tegra_dsi_set_dc_clk(struct tegra_dc *dc, shift_clk_div_register = 0; #endif + val = PIXEL_CLK_DIVIDER_PCD1 | + SHIFT_CLK_DIVIDER(shift_clk_div_register + 2); + + /* SW WAR for bug 1045373. To make the shift clk dividor effect under + * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it. + * After 2us delay, write the target values to it. */ +#if defined(CONFIG_ARCH_TEGRA_11x_SOC) + tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL); + tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + + udelay(2); +#endif + /* TODO: find out if PCD3 option is required */ val = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(shift_clk_div_register); + tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL); } diff --git a/drivers/video/tegra/dc/mode.c b/drivers/video/tegra/dc/mode.c index 4d3e06837ffd..139550d21b15 100644 --- a/drivers/video/tegra/dc/mode.c +++ b/drivers/video/tegra/dc/mode.c @@ -19,6 +19,7 @@ #include <linux/err.h> #include <linux/types.h> #include <linux/clk.h> +#include <linux/delay.h> #include <mach/clk.h> #include <mach/dc.h> @@ -252,8 +253,24 @@ int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode) div = (rate * 2 / pclk) - 2; + /* SW WAR for bug 1045373. To make the shift clk dividor effect under + * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it. + * After 2us delay, write the target values to it. */ +#if defined(CONFIG_ARCH_TEGRA_11x_SOC) + tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div + 2), + DC_DISP_DISP_CLOCK_CONTROL); + tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL); + tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); + + udelay(2); +#endif + +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) + /* Deprecated on t11x. */ tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS); +#endif + tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div), DC_DISP_DISP_CLOCK_CONTROL); |