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authorXinyu Chen <xinyu.chen@freescale.com>2010-03-18 09:15:21 +0800
committerAlejandro Gonzalez <alex.gonzalez@digi.com>2010-05-25 11:20:14 +0200
commitc497db9c822aa9ff9b49d4bb668974ecc5013aaf (patch)
treee79e6aea0ce19356745e03b086aa319b46704236 /drivers
parent8513c72819be22b22d044424eff0fd4183ea8ca2 (diff)
ENGR00121653 MX53 Add FEC support
Add FEC support for MX53 EVK Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com> Signed-off-by: Alejandro Gonzalez <alex.gonzalez@digi.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/net/fec.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index f5ef6b5c3e07..60d8f3694644 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -2000,7 +2000,9 @@ fec_restart(struct net_device *dev, int duplex)
writel(0, fep->hwp + FEC_HASH_TABLE_LOW);
#endif
#ifdef CONFIG_ARCH_MXC
- if (cpu_is_mx25()) {
+ if (cpu_is_mx25() || cpu_is_mx53()) {
+
+ unsigned int val;
/*
* Set up the MII gasket for RMII mode
*/
@@ -2011,11 +2013,18 @@ fec_restart(struct net_device *dev, int duplex)
while (__raw_readl(fep->hwp + FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
udelay(1);
+ val = FEC_MIIGSK_CFGR_IF_MODE_RMII;
+ if (cpu_is_mx53() &&
+ fep->phy_status & (PHY_STAT_10FDX | PHY_STAT_10HDX)) /* 10Mb */
+ val |= FEC_MIIGSK_CFGR_FRCONT;
/* configure the gasket for RMII, 50 MHz, no loopback, no echo */
- __raw_writel(FEC_MIIGSK_CFGR_IF_MODE_RMII, fep->hwp + FEC_MIIGSK_CFGR);
+ __raw_writel(val, fep->hwp + FEC_MIIGSK_CFGR);
/* re-enable the gasket */
__raw_writel(FEC_MIIGSK_ENR_EN, fep->hwp + FEC_MIIGSK_ENR);
+ while (!(__raw_readl(fep->hwp + FEC_MIIGSK_ENR)
+ & FEC_MIIGSK_ENR_READY))
+ udelay(1);
}
#endif
/* Set maximum receive buffer size. */