diff options
| author | Rhyland Klein <rklein@nvidia.com> | 2013-12-26 16:44:22 -0800 |
|---|---|---|
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | 2014-02-17 16:18:06 +0200 |
| commit | 67fc26bfd7a265883fd0804f24f6287d16769e3d (patch) | |
| tree | c538943e3b3353211949e669e90e7b6e8945063c /drivers | |
| parent | 2ec35fd503bf6367ba55ed94dcb68edfe0d26e6a (diff) | |
clk: tegra: Fix PLLD mnp table
PLLD was using the same mnp table as PLLP. Fix it to use its own
table which is different from PLLP's.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/clk/tegra/clk-tegra124.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c index 28bb238d9807..14c3f2fb6047 100644 --- a/drivers/clk/tegra/clk-tegra124.c +++ b/drivers/clk/tegra/clk-tegra124.c @@ -570,6 +570,15 @@ static struct tegra_clk_pll_params pll_a_params = { .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK, }; +static struct div_nmp plld_nmp = { + .divm_shift = 0, + .divm_width = 5, + .divn_shift = 8, + .divn_width = 11, + .divp_shift = 20, + .divp_width = 3, +}; + static struct tegra_clk_pll_freq_table pll_d_freq_table[] = { {12000000, 216000000, 864, 12, 4, 12}, {13000000, 216000000, 864, 13, 4, 12}, @@ -603,7 +612,7 @@ static struct tegra_clk_pll_params pll_d_params = { .lock_mask = PLL_BASE_LOCK, .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE, .lock_delay = 1000, - .div_nmp = &pllp_nmp, + .div_nmp = &plld_nmp, .freq_table = pll_d_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON | TEGRA_PLL_USE_LOCK, |