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authorStefan Agner <stefan@agner.ch>2014-10-03 15:01:34 +0200
committerStefan Agner <stefan@agner.ch>2014-10-03 15:28:29 +0200
commit051d9721a6515e188a3c8e1a60428eb2f8f8a2de (patch)
tree96ad77a0656aee2ac62c3d0a84c90ddef8f04401 /firmware/README.AddingFirmware
parent2b2244a3e7c3d537f436a3580999b3032628d17d (diff)
ARM: imx: clk-vf610: define PLL's clock treearchive/vf610-clk-pll-fixes-v1
So far, the required PLL's (PLL1/PLL2/PLL5) have been initialized by boot loader and the kernel code defined fixed rates according to those default configurations. Beginning with the USB PLL7 the code started to initialize the PLL's itself (using imx_clk_pllv3). However, since commit dc4805c2e78ba5a22ea1632f3e3e4ee601a1743b (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver) imx_clk_pllv3 no longer takes care of the ENABLE and BYPASS bits, hence the USB PLL were not configured correctly anymore. This patch not only fixes those USB PLL's, but also makes use of the imx_clk_pllv3 for all PLL's and alignes the code with the PLL support of the i.MX6 series.
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