diff options
| author | Ranjani Vaidyanathan <ra5478@freescale.com> | 2011-10-19 14:38:19 -0500 |
|---|---|---|
| committer | Jason Liu <r64343@freescale.com> | 2012-07-20 13:16:49 +0800 |
| commit | 9f27f73686cea1a8f64d5529c1f34aba88a5a638 (patch) | |
| tree | e69364c38524362f78dec34886460b286ae4257a /fs/jfs/jfs_incore.h | |
| parent | cca77ce5e8c38ee163b82539be8050fc3fa9098d (diff) | |
ENGR00160492: MX6-Disable PLL1 when CPU clk is below 400MHz.
When CPU frequency is below 400MHz (due to CPUFREQ or dvfs-core), we can source
pll1_sw_clk from PLL2_PFD_400M and disable PLL1. This can save some power.
Fixed warnings in dvfs_core driver.
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Diffstat (limited to 'fs/jfs/jfs_incore.h')
0 files changed, 0 insertions, 0 deletions