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authorChew, Chiau Ee <chiau.ee.chew@intel.com>2013-09-27 02:57:35 +0800
committerWolfram Sang <wsa@the-dreams.de>2013-09-27 18:12:31 +0200
commitbd63ace4dc4290165bbf3bf546eba50453d0aa9d (patch)
tree943d8582cc7cd5fb470b816d4ac6df7c600084ea /fs/select.c
parent85b3a9356e84f683dd27fe8b73ad15608b4fc2c5 (diff)
i2c: designware: 10-bit addressing mode enabling if I2C_DYNAMIC_TAR_UPDATE is set
According to Designware I2C spec, if I2C_DYNAMIC_TAR_UPDATE is set to 1, the 10-bit addressing mode is controlled by IC_10BITADDR_MASTER bit of IC_TAR register instead of IC_CON register. The IC_10BITADDR_MASTER in IC_CON register becomes read-only copy. Since I2C_DYNAMIC_TAR_UPDATE value can't be detected from hardware register, so we will always set the IC_10BITADDR_MASTER bit in both IC_CON and IC_TAR register whenever 10-bit addresing mode is requested by user application. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'fs/select.c')
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