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authorAlex Frid <afrid@nvidia.com>2011-06-08 18:39:10 -0700
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:45:57 -0800
commit254fd2edaf3a7a627274d105f5644df24feedebd (patch)
treeb51d8c6ddf4218b35e407a504d8dbb4020cf1a1a /fs
parentc009bf9fb07438018c27bed99ce5c44ad996a4e6 (diff)
ARM: tegra: dvfs: Update Tegra3 EMC DFS
Updated Tegra3 EMC DFS table to match new PLLP base frequency (408MHz) and enable power saving features. Bug 836260 Change-Id: Ie85cda67804ea29a0df475464020b1e76176ea3b Reviewed-on: http://git-master/r/36049 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Scott Williams <scwilliams@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Rebase-Id: Rdbb0343817c2aee5506f5ca78ead4807d4c76182
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