diff options
| author | Len Brown <len.brown@intel.com> | 2005-09-08 01:45:47 -0400 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2005-09-08 01:45:47 -0400 |
| commit | 64e47488c913ac704d465a6af86a26786d1412a5 (patch) | |
| tree | d3b0148592963dcde26e4bb35ddfec8b1eaf8e23 /include/asm-alpha/auxvec.h | |
| parent | 4a35a46bf1cda4737c428380d1db5d15e2590d18 (diff) | |
| parent | caf39e87cc1182f7dae84eefc43ca14d54c78ef9 (diff) | |
Merge linux-2.6 with linux-acpi-2.6
Diffstat (limited to 'include/asm-alpha/auxvec.h')
| -rw-r--r-- | include/asm-alpha/auxvec.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/asm-alpha/auxvec.h b/include/asm-alpha/auxvec.h new file mode 100644 index 000000000000..e96fe880e310 --- /dev/null +++ b/include/asm-alpha/auxvec.h @@ -0,0 +1,24 @@ +#ifndef __ASM_ALPHA_AUXVEC_H +#define __ASM_ALPHA_AUXVEC_H + +/* Reserve these numbers for any future use of a VDSO. */ +#if 0 +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 +#endif + +/* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the + value is -1, then the cache doesn't exist. Otherwise: + + bit 0-3: Cache set-associativity; 0 means fully associative. + bit 4-7: Log2 of cacheline size. + bit 8-31: Size of the entire cache >> 8. + bit 32-63: Reserved. +*/ + +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 +#define AT_L3_CACHESHAPE 37 + +#endif /* __ASM_ALPHA_AUXVEC_H */ |