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authorAndrew Victor <andrew@sanpeople.com>2007-07-16 11:55:42 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-20 09:43:28 +0100
commited54fcfd785e8fecfbd8b129466235fc4ab0a402 (patch)
tree4d02bcd19951cf17eaf82f4987d608b80b90315a /include/asm-arm
parentc06911c00b2af93e498ba45200ad903929e71529 (diff)
[ARM] 4479/1: AT91: Define new MMC register bits
Add definitions for RDPROOF, WRPROOF and PDCFBYTE bits of the Mode Register in the updated MMC controller found on the AT91SAM9260 and AT91SAM9263 processors. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-at91/at91_mci.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index 40a9876b661a..c2e11cc374ba 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -26,6 +26,9 @@
#define AT91_MCI_MR 0x04 /* Mode Register */
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
+#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
+#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
+#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */