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authorGraf Yang <graf.yang@analog.com>2008-04-24 04:43:14 +0800
committerBryan Wu <cooloney@kernel.org>2008-04-24 04:43:14 +0800
commit6ed839423073251b513664fdadb180634aed704b (patch)
tree073350299070ba091f4fb4fb146b9a931edc44b8 /include/asm-blackfin/mach-bf533
parentdb68254f0639a357309f02cf8707490265fa7a31 (diff)
[Blackfin] arch: Resolve the clash issue of UART defines between blackfin headers and include/linux/serial_reg.
Signed-off-by: Graf Yang <graf.yang@analog.com> Cc: Robin Getz <rgetz@blackfin.uclinux.org> Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'include/asm-blackfin/mach-bf533')
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h29
1 files changed, 17 insertions, 12 deletions
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 37134aaf9954..17e1548cec08 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -88,20 +88,25 @@
#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */
/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR 0xFFC00400 /* Transmit Holding register */
-#define UART_RBR 0xFFC00400 /* Receive Buffer register */
-#define UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART_IER 0xFFC00404 /* Interrupt Enable Register */
-#define UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART_IIR 0xFFC00408 /* Interrupt Identification Register */
-#define UART_LCR 0xFFC0040C /* Line Control Register */
-#define UART_MCR 0xFFC00410 /* Modem Control Register */
-#define UART_LSR 0xFFC00414 /* Line Status Register */
+
+/*
+ * Because include/linux/serial_reg.h have defined UART_*,
+ * So we define blackfin uart regs to BFIN_UART_*.
+ */
+#define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */
+#define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */
+#define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
+#define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */
+#define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
+#define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */
+#define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */
+#define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */
+#define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */
#if 0
-#define UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
+#define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */
#endif
-#define UART_SCR 0xFFC0041C /* SCR Scratch Register */
-#define UART_GCTL 0xFFC00424 /* Global Control Register */
+#define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */
+#define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */
/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
#define SPI0_REGBASE 0xFFC00500