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authorRobin Getz <robin.getz@analog.com>2007-10-10 23:55:26 +0800
committerBryan Wu <bryan.wu@analog.com>2007-10-10 23:55:26 +0800
commit3bebca2d20796dd3dc62c5d3e74148087c7ce5bd (patch)
treefdb5eb8eb774fa5e8df41ebbf0e0d2c82b9ff627 /include/asm-blackfin/mach-bf537
parenta298049180d2c56fc8ac1796b24973bf4f019cc7 (diff)
Blackfin arch: to do some consolidation of common code and common name spaces
now all BLKFIN should be BFIN, should be no functional changes. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin/mach-bf537')
-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h1
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h67
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h60
3 files changed, 37 insertions, 91 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 3803f156bf1c..e377064b307c 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -133,6 +133,7 @@
/* Anomalies that don't exist on this proc */
#define ANOMALY_05000125 (0)
+#define ANOMALY_05000158 (0)
#define ANOMALY_05000183 (0)
#define ANOMALY_05000198 (0)
#define ANOMALY_05000266 (0)
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
index 603823f51ca0..cfe2a221112e 100644
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -62,12 +62,12 @@
/***************************/
-#define BLKFIN_DSUBBANKS 4
-#define BLKFIN_DWAYS 2
-#define BLKFIN_DLINES 64
-#define BLKFIN_ISUBBANKS 4
-#define BLKFIN_IWAYS 4
-#define BLKFIN_ILINES 32
+#define BFIN_DSUBBANKS 4
+#define BFIN_DWAYS 2
+#define BFIN_DLINES 64
+#define BFIN_ISUBBANKS 4
+#define BFIN_IWAYS 4
+#define BFIN_ILINES 32
#define WAY0_L 0x1
#define WAY1_L 0x2
@@ -138,59 +138,4 @@
#define CPUID 0x0
#endif
-#if (CONFIG_MEM_SIZE % 4)
-#error "SDRAM mem size must be multible of 4MB"
-#endif
-
-#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
-
-#define ANOMALY_05000158_WORKAROUND 0x200
-#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
- | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else /*Write Through */
-#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
- | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#endif
-
-
-#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
-#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
-#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
-
-#define SIZE_1K 0x00000400 /* 1K */
-#define SIZE_4K 0x00001000 /* 4K */
-#define SIZE_1M 0x00100000 /* 1M */
-#define SIZE_4M 0x00400000 /* 4M */
-
-#define MAX_CPLBS (16 * 2)
-
-/*
-* Number of required data CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 16 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Data Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-* 1 for ASYNC Memory
-*/
-
-
-#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
-
-/*
-* Number of required instruction CPLB switchtable entries
-* MEMSIZE / 4 (we mostly install 4M page size CPLBs
-* approx 12 for smaller 1MB page size CPLBs for allignment purposes
-* 1 for L1 Instruction Memory
-* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
-*/
-
-#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
-
#endif /* __MACH_BF537_H__ */
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 2a808c1202bf..18759e38eaae 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -52,10 +52,10 @@
/* Memory Map for ADSP-BF537 processors */
-#ifdef CONFIG_BLKFIN_CACHE
-#define BLKFIN_ICACHESIZE (16*1024)
+#ifdef CONFIG_BFIN_ICACHE
+#define BFIN_ICACHESIZE (16*1024)
#else
-#define BLKFIN_ICACHESIZE (0*1024)
+#define BFIN_ICACHESIZE (0*1024)
#endif
@@ -66,29 +66,29 @@
#define L1_CODE_LENGTH 0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000
-#define BLKFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS 1
+#define BFIN_DCACHESIZE (16*1024)
+#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS 2
+#define BFIN_DCACHESIZE (32*1024)
+#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000
-#define BLKFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS 0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#define BFIN_DCACHESIZE (0*1024)
+#define BFIN_DSUPBANKS 0
+#endif /*CONFIG_BFIN_DCACHE*/
#endif /*CONFIG_BF537*/
@@ -102,30 +102,30 @@
#define L1_CODE_LENGTH 0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH 0x4000
-#define BLKFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS 1
+#define BFIN_DCACHESIZE (16*1024)
+#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
-#define BLKFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS 2
+#define BFIN_DCACHESIZE (32*1024)
+#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x4000
#define L1_DATA_B_LENGTH 0x4000
-#define BLKFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS 0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#define BFIN_DCACHESIZE (0*1024)
+#define BFIN_DSUPBANKS 0
+#endif /*CONFIG_BFIN_DCACHE*/
#endif
@@ -138,30 +138,30 @@
#define L1_CODE_LENGTH 0xC000
-#ifdef CONFIG_BLKFIN_DCACHE
+#ifdef CONFIG_BFIN_DCACHE
-#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#ifdef CONFIG_BFIN_DCACHE_BANKA
#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH 0x8000
-#define BLKFIN_DCACHESIZE (16*1024)
-#define BLKFIN_DSUPBANKS 1
+#define BFIN_DCACHESIZE (16*1024)
+#define BFIN_DSUPBANKS 1
#else
#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
-#define BLKFIN_DCACHESIZE (32*1024)
-#define BLKFIN_DSUPBANKS 2
+#define BFIN_DCACHESIZE (32*1024)
+#define BFIN_DSUPBANKS 2
#endif
#else
#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
#define L1_DATA_A_LENGTH 0x8000
#define L1_DATA_B_LENGTH 0x8000
-#define BLKFIN_DCACHESIZE (0*1024)
-#define BLKFIN_DSUPBANKS 0
-#endif /*CONFIG_BLKFIN_DCACHE*/
+#define BFIN_DCACHESIZE (0*1024)
+#define BFIN_DSUPBANKS 0
+#endif /*CONFIG_BFIN_DCACHE*/
#endif