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authorSonic Zhang <sonic.zhang@analog.com>2007-12-23 23:02:13 +0800
committerBryan Wu <bryan.wu@analog.com>2007-12-23 23:02:13 +0800
commitfb5f00492a748facc9f069c95621e05c148edf53 (patch)
treecf93dbf8140279e4913eb421dd68922a76ba241f /include/asm-blackfin
parentc50e19f49830fb651b4b702ad2c3abcdf110b576 (diff)
[Blackfin] arch: Fix bug to Enable kernel to build for bf548 with PM.
On BF548-EZKIT, build kernel faills with power management, video and audio enabled. This patch fix this. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include/asm-blackfin')
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h1
2 files changed, 3 insertions, 2 deletions
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 9fb7bc5399a8..c34507a3f1df 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -88,7 +88,7 @@ Events (highest priority) EMU 0
#define IRQ_PINT1 BFIN_IRQ(20) /* PINT1 Interrupt */
#define IRQ_MDMAS0 BFIN_IRQ(21) /* MDMA Stream 0 Interrupt */
#define IRQ_MDMAS1 BFIN_IRQ(22) /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCHDOG BFIN_IRQ(23) /* Watchdog Interrupt */
+#define IRQ_WATCH BFIN_IRQ(23) /* Watchdog Interrupt */
#define IRQ_DMAC1_ERROR BFIN_IRQ(24) /* DMAC1 Status (Error) Interrupt */
#define IRQ_SPORT2_ERROR BFIN_IRQ(25) /* SPORT2 Error Interrupt */
#define IRQ_SPORT3_ERROR BFIN_IRQ(26) /* SPORT3 Error Interrupt */
@@ -406,7 +406,7 @@ Events (highest priority) EMU 0
#define IRQ_PINT1_POS 16
#define IRQ_MDMAS0_POS 20
#define IRQ_MDMAS1_POS 24
-#define IRQ_WATCHDOG_POS 28
+#define IRQ_WATCH_POS 28
/* IAR3 BIT FIELDS */
#define IRQ_DMAC1_ERR_POS 0
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index 0cb279e973d7..e792eb7ae6a0 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -30,6 +30,7 @@
*/
#if (CONFIG_MEM_MT46V32M16)
+#endif
#if defined CONFIG_CLKIN_HALF
#define CLKIN_HALF 1