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authorRalf Baechle <ralf@linux-mips.org>2005-06-15 13:00:12 +0000
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 19:31:23 +0100
commit02416dcf5a94af34bcd28b4baf25bbbf399d8136 (patch)
tree1906c4266d4e28ef0b13d0579a145603dcbcff1b /include/asm-mips/cpu-features.h
parentaac8aa7717a23a9bf8740dbfb59755b1d62f04bf (diff)
Redo RM9000 workaround which along with other DSP ASE changes was
causing some headache for debuggers knowing about signal frames. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/cpu-features.h')
-rw-r--r--include/asm-mips/cpu-features.h11
1 files changed, 0 insertions, 11 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index 4930824a43aa..bb2212cf460a 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -109,17 +109,6 @@
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
#endif
-/*
- * Certain CPUs may throw bizarre exceptions if not the whole cacheline
- * contains valid instructions. For these we ensure proper alignment of
- * signal trampolines and pad them to the size of a full cache lines with
- * nops. This is also used in structure definitions so can't be a test macro
- * like the others.
- */
-#ifndef PLAT_TRAMPOLINE_STUFF_LINE
-#define PLAT_TRAMPOLINE_STUFF_LINE 0UL
-#endif
-
#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)