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| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-29 13:44:45 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-29 13:44:45 -0700 |
| commit | 8d231c11fd0b694c447e59e687754b6999eea0a2 (patch) | |
| tree | b0b3c17efff7018bbf948e489f642c8079f33cc0 /include/asm-mips/cpu-features.h | |
| parent | 1f1332f727c3229eb2166a83fec5d3de6a73dce2 (diff) | |
| parent | 8db089c6b5594c961fb6bc6d613b9926e0d3d98f (diff) | |
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (33 commits)
[MIPS] Add missing backslashes to macro definitions.
[MIPS] Death list of board support to be removed after 2.6.18.
[MIPS] Remove BSD and Sys V compat data types.
[MIPS] ioc3.h: Uses u8, so include <linux/types.h>.
[MIPS] 74K: Assume it will also have an AR bit in config7
[MIPS] Treat CPUs with AR bit as physically indexed.
[MIPS] Oprofile: Support VSMP on 34K.
[MIPS] MIPS32/MIPS64 S-cache fix and cleanup
[MIPS] excite: PCI makefile needs to use += if it wants a chance to work.
[MIPS] excite: plat_setup -> plat_mem_setup.
[MIPS] au1xxx: export dbdma functions
[MIPS] au1xxx: dbdma, no sleeping under spin_lock
[MIPS] au1xxx: fix PSC_SMBTXRX_RSR.
[MIPS] Early printk for IP27.
[MIPS] Fix handling of 0 length I & D caches.
[MIPS] Typo fixes.
[MIPS] MIPS32/MIPS64 secondary cache management
[MIPS] Fix FIXADDR_TOP for TX39/TX49.
[MIPS] Remove first timer interrupt setup in wrppmc_timer_setup()
[MIPS] Fix configuration of R2 CPU features and multithreading.
...
Diffstat (limited to 'include/asm-mips/cpu-features.h')
| -rw-r--r-- | include/asm-mips/cpu-features.h | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h index 881ce1f9803d..44285a9d5520 100644 --- a/include/asm-mips/cpu-features.h +++ b/include/asm-mips/cpu-features.h @@ -187,19 +187,15 @@ # endif #endif -#ifdef CONFIG_CPU_MIPSR2 -# if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) -# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) -# else -# define cpu_has_vint 0 -# endif -# if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) -# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) -# else -# define cpu_has_veic 0 -# endif -#else +#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) +# define cpu_has_vint (cpu_data[0].options & MIPS_CPU_VINT) +#elif !defined(cpu_has_vint) # define cpu_has_vint 0 +#endif + +#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) +# define cpu_has_veic (cpu_data[0].options & MIPS_CPU_VEIC) +#elif !defined(cpu_has_veic) # define cpu_has_veic 0 #endif |