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authorRalf Baechle <ralf@linux-mips.org>2007-07-14 13:24:05 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-07-20 18:57:39 +0100
commit17099b1142f6c0359fca60a3464dea8fb30badea (patch)
tree26b9f3955dca84ccab594a76680c2a71e166768a /include/asm-mips/system.h
parented203dadcd1373e80e95b04075e1eefc554a914b (diff)
[MIPS] Make support for weakly ordered LL/SC a config option.
None of weakly ordered processor supported in tree need this but it seems like this could change ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include/asm-mips/system.h')
-rw-r--r--include/asm-mips/system.h8
1 files changed, 4 insertions, 4 deletions
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 76339165bc20..eba2e3da9abe 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -117,7 +117,7 @@ static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
raw_local_irq_restore(flags); /* implies memory barrier */
}
- smp_mb();
+ smp_llsc_mb();
return retval;
}
@@ -165,7 +165,7 @@ static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
raw_local_irq_restore(flags); /* implies memory barrier */
}
- smp_mb();
+ smp_llsc_mb();
return retval;
}
@@ -246,7 +246,7 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
raw_local_irq_restore(flags); /* implies memory barrier */
}
- smp_mb();
+ smp_llsc_mb();
return retval;
}
@@ -352,7 +352,7 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
raw_local_irq_restore(flags); /* implies memory barrier */
}
- smp_mb();
+ smp_llsc_mb();
return retval;
}