diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2008-07-29 08:09:44 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-07-29 08:09:44 +0900 |
| commit | f15cbe6f1a4b4d9df59142fc8e4abb973302cf44 (patch) | |
| tree | 774d7b11abaaf33561ab8268bf51ddd9ceb79025 /include/asm-sh/cpu-sh4/cache.h | |
| parent | 25326277d8d1393d1c66240e6255aca780f9e3eb (diff) | |
sh: migrate to arch/sh/include/
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac.
Most of the moving about was done with Sam's directions at:
http://marc.info/?l=linux-sh&m=121724823706062&w=2
with subsequent hacking and fixups entirely my fault.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/cpu-sh4/cache.h')
| -rw-r--r-- | include/asm-sh/cpu-sh4/cache.h | 42 |
1 files changed, 0 insertions, 42 deletions
diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h deleted file mode 100644 index 1c61ebf5c8e3..000000000000 --- a/include/asm-sh/cpu-sh4/cache.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-sh/cpu-sh4/cache.h - * - * Copyright (C) 1999 Niibe Yutaka - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_CPU_SH4_CACHE_H -#define __ASM_CPU_SH4_CACHE_H - -#define L1_CACHE_SHIFT 5 - -#define SH_CACHE_VALID 1 -#define SH_CACHE_UPDATED 2 -#define SH_CACHE_COMBINED 4 -#define SH_CACHE_ASSOC 8 - -#define CCR 0xff00001c /* Address of Cache Control Register */ -#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ -#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ -#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ -#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */ -#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */ -#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */ -#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */ -#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */ -#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */ -#ifndef CONFIG_CPU_SH4A -#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */ -#endif - -/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */ -#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE) -#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI) - -#define CACHE_IC_ADDRESS_ARRAY 0xf0000000 -#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 - -#endif /* __ASM_CPU_SH4_CACHE_H */ - |