Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

3 files changed, 102 insertions, 0 deletions

diff --git a/include/asm-sh/dreamcast/dma.h b/include/asm-sh/dreamcast/dma.h
new file mode 100644
index 000000000000..ddd68e788705
--- /dev/null
+++ b/include/asm-sh/dreamcast/dma.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-sh/dreamcast/dma.h
+ *
+ * Copyright (C) 2003 Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DREAMCAST_DMA_H
+#define __ASM_SH_DREAMCAST_DMA_H
+
+/* Number of DMA channels */
+#define ONCHIP_NR_DMA_CHANNELS	4
+#define G2_NR_DMA_CHANNELS	4
+#define PVR2_NR_DMA_CHANNELS	1
+
+/* Channels for cascading */
+#define PVR2_CASCADE_CHAN	2
+#define G2_CASCADE_CHAN		3
+
+/* PVR2 DMA Registers */
+#define PVR2_DMA_BASE		0xa05f6800
+#define PVR2_DMA_ADDR		(PVR2_DMA_BASE + 0)
+#define PVR2_DMA_COUNT		(PVR2_DMA_BASE + 4)
+#define PVR2_DMA_MODE		(PVR2_DMA_BASE + 8)
+#define PVR2_DMA_LMMODE0	(PVR2_DMA_BASE + 132)
+#define PVR2_DMA_LMMODE1	(PVR2_DMA_BASE + 136)
+
+/* G2 DMA Register */
+#define G2_DMA_BASE		0xa05f7800
+
+#endif /* __ASM_SH_DREAMCAST_DMA_H */
+
diff --git a/include/asm-sh/dreamcast/pci.h b/include/asm-sh/dreamcast/pci.h
new file mode 100644
index 000000000000..e401b24b0d8e
--- /dev/null
+++ b/include/asm-sh/dreamcast/pci.h
@@ -0,0 +1,25 @@
+/*
+ * include/asm-sh/dreamcast/pci.h
+ *
+ * Copyright (C) 2001, 2002  M. R. Brown
+ * Copyright (C) 2002, 2003  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_SH_DREAMCAST_PCI_H
+#define __ASM_SH_DREAMCAST_PCI_H
+
+#include <asm/mach/sysasic.h>
+
+#define	GAPSPCI_REGS		0x01001400
+#define GAPSPCI_DMA_BASE	0x01840000
+#define GAPSPCI_DMA_SIZE	32768
+#define GAPSPCI_BBA_CONFIG	0x01001600
+#define GAPSPCI_BBA_CONFIG_SIZE	0x2000
+
+#define	GAPSPCI_IRQ		HW_EVENT_EXTERNAL
+
+#endif /* __ASM_SH_DREAMCAST_PCI_H */
+
diff --git a/include/asm-sh/dreamcast/sysasic.h b/include/asm-sh/dreamcast/sysasic.h
new file mode 100644
index 000000000000..c8858537803c
--- /dev/null
+++ b/include/asm-sh/dreamcast/sysasic.h
@@ -0,0 +1,43 @@
+/* include/asm-sh/dc_sysasic.h
+ *
+ * Definitions for the Dreamcast System ASIC and related peripherals.
+ *
+ * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
+ * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
+ *
+ * This file is part of the LinuxDC project (www.linuxdc.org)
+ *
+ * Released under the terms of the GNU GPL v2.0.
+ *
+ */
+#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
+#define __ASM_SH_DREAMCAST_SYSASIC_H
+
+#include <asm/irq.h>
+
+/* Hardware events -
+
+   Each of these events correspond to a bit within the Event Mask Registers/
+   Event Status Registers.  Because of the virtual IRQ numbering scheme, a
+   base offset must be used when calculating the virtual IRQ that each event
+   takes.
+*/
+
+#define HW_EVENT_IRQ_BASE  OFFCHIP_IRQ_BASE /* 48 */
+
+/* IRQ 13 */
+#define HW_EVENT_VSYNC     (HW_EVENT_IRQ_BASE +  5) /* VSync */
+#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
+#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
+#define HW_EVENT_G2_DMA    (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
+#define HW_EVENT_PVR2_DMA  (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
+
+/* IRQ 11 */
+#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
+#define HW_EVENT_AICA_SYS  (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
+#define HW_EVENT_EXTERNAL  (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
+
+#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
+
+#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */
+