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authorMagnus Damm <damm@igel.co.jp>2007-08-12 15:26:12 +0900
committerPaul Mundt <lethal@linux-sh.org>2007-09-21 11:57:50 +0900
commit73505b445dbb8ad12df468404c4dd5cde9c40c65 (patch)
treec248710475090f01dc874e2c878efc769b24d2af /include/asm-sh/hw_irq.h
parent6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (diff)
sh: intc - rework core code
This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/asm-sh/hw_irq.h')
-rw-r--r--include/asm-sh/hw_irq.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h
index 6c759b2b8929..0e6a60304974 100644
--- a/include/asm-sh/hw_irq.h
+++ b/include/asm-sh/hw_irq.h
@@ -75,7 +75,7 @@ struct intc_desc {
unsigned int nr_prio_regs;
struct intc_sense_reg *sense_regs;
unsigned int nr_sense_regs;
- struct irq_chip chip;
+ char *name;
};
#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
@@ -86,7 +86,7 @@ struct intc_desc symbol = { \
_INTC_ARRAY(priorities), \
_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
_INTC_ARRAY(sense_regs), \
- .chip.name = chipname, \
+ chipname, \
}
void __init register_intc_controller(struct intc_desc *desc);