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author | Jeff Garzik <jgarzik@pretzel.yyz.us> | 2005-06-26 23:42:30 -0400 |
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committer | Jeff Garzik <jgarzik@pobox.com> | 2005-06-26 23:42:30 -0400 |
commit | f45727d52d1581e9ff4df9d1a12a60789ad2d1eb (patch) | |
tree | 773ae25f98542e6d382c688f7e85e8137d065614 /include/asm-sparc64/processor.h | |
parent | 4c925f452cfd16c690209e96821ee094e09a2404 (diff) | |
parent | 5696c1944a33b4434a9a1ebb6383b906afd43a10 (diff) |
Merge /spare/repo/netdev-2.6/ branch 'ieee80211'
Diffstat (limited to 'include/asm-sparc64/processor.h')
-rw-r--r-- | include/asm-sparc64/processor.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/asm-sparc64/processor.h b/include/asm-sparc64/processor.h index bc1445b904ef..d0bee2413560 100644 --- a/include/asm-sparc64/processor.h +++ b/include/asm-sparc64/processor.h @@ -192,6 +192,40 @@ extern unsigned long get_wchan(struct task_struct *task); #define cpu_relax() barrier() +/* Prefetch support. This is tuned for UltraSPARC-III and later. + * UltraSPARC-I will treat these as nops, and UltraSPARC-II has + * a shallower prefetch queue than later chips. + */ +#define ARCH_HAS_PREFETCH +#define ARCH_HAS_PREFETCHW +#define ARCH_HAS_SPINLOCK_PREFETCH + +static inline void prefetch(const void *x) +{ + /* We do not use the read prefetch mnemonic because that + * prefetches into the prefetch-cache which only is accessible + * by floating point operations in UltraSPARC-III and later. + * By contrast, "#one_write" prefetches into the L2 cache + * in shared state. + */ + __asm__ __volatile__("prefetch [%0], #one_write" + : /* no outputs */ + : "r" (x)); +} + +static inline void prefetchw(const void *x) +{ + /* The most optimal prefetch to use for writes is + * "#n_writes". This brings the cacheline into the + * L2 cache in "owned" state. + */ + __asm__ __volatile__("prefetch [%0], #n_writes" + : /* no outputs */ + : "r" (x)); +} + +#define spin_lock_prefetch(x) prefetchw(x) + #endif /* !(__ASSEMBLY__) */ #endif /* !(__ASM_SPARC64_PROCESSOR_H) */ |