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authorDavid S. Miller <davem@sunset.davemloft.net>2007-10-27 00:13:04 -0700
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-27 00:13:04 -0700
commitd979f1792d1a4867eda0028b3aac8c6d4a535bb7 (patch)
tree89a8a9471ad2fa57f7349426ac62d14f3f134c63 /include/asm-sparc64/spitfire.h
parentec3b67c11df42362ccda81261d62829042f223f0 (diff)
[SPARC64]: __inline__ --> inline
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include/asm-sparc64/spitfire.h')
-rw-r--r--include/asm-sparc64/spitfire.h53
1 files changed, 26 insertions, 27 deletions
diff --git a/include/asm-sparc64/spitfire.h b/include/asm-sparc64/spitfire.h
index cf7807813e85..63b7040e8134 100644
--- a/include/asm-sparc64/spitfire.h
+++ b/include/asm-sparc64/spitfire.h
@@ -1,7 +1,6 @@
-/* $Id: spitfire.h,v 1.18 2001/11/29 16:42:10 kanoj Exp $
- * spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
+/* spitfire.h: SpitFire/BlackBird/Cheetah inline MMU operations.
*
- * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
+ * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
*/
#ifndef _SPARC64_SPITFIRE_H
@@ -67,7 +66,7 @@ extern void cheetah_enable_pcache(void);
/* The data cache is write through, so this just invalidates the
* specified line.
*/
-static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
+static inline void spitfire_put_dcache_tag(unsigned long addr, unsigned long tag)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -81,7 +80,7 @@ static __inline__ void spitfire_put_dcache_tag(unsigned long addr, unsigned long
* a flush instruction (to any address) is sufficient to handle
* this issue after the line is invalidated.
*/
-static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
+static inline void spitfire_put_icache_tag(unsigned long addr, unsigned long tag)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -89,7 +88,7 @@ static __inline__ void spitfire_put_icache_tag(unsigned long addr, unsigned long
: "r" (tag), "r" (addr), "i" (ASI_IC_TAG));
}
-static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
+static inline unsigned long spitfire_get_dtlb_data(int entry)
{
unsigned long data;
@@ -103,7 +102,7 @@ static __inline__ unsigned long spitfire_get_dtlb_data(int entry)
return data;
}
-static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
+static inline unsigned long spitfire_get_dtlb_tag(int entry)
{
unsigned long tag;
@@ -113,7 +112,7 @@ static __inline__ unsigned long spitfire_get_dtlb_tag(int entry)
return tag;
}
-static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
+static inline void spitfire_put_dtlb_data(int entry, unsigned long data)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -122,7 +121,7 @@ static __inline__ void spitfire_put_dtlb_data(int entry, unsigned long data)
"i" (ASI_DTLB_DATA_ACCESS));
}
-static __inline__ unsigned long spitfire_get_itlb_data(int entry)
+static inline unsigned long spitfire_get_itlb_data(int entry)
{
unsigned long data;
@@ -136,7 +135,7 @@ static __inline__ unsigned long spitfire_get_itlb_data(int entry)
return data;
}
-static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
+static inline unsigned long spitfire_get_itlb_tag(int entry)
{
unsigned long tag;
@@ -146,7 +145,7 @@ static __inline__ unsigned long spitfire_get_itlb_tag(int entry)
return tag;
}
-static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
+static inline void spitfire_put_itlb_data(int entry, unsigned long data)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -155,7 +154,7 @@ static __inline__ void spitfire_put_itlb_data(int entry, unsigned long data)
"i" (ASI_ITLB_DATA_ACCESS));
}
-static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
+static inline void spitfire_flush_dtlb_nucleus_page(unsigned long page)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
@@ -163,7 +162,7 @@ static __inline__ void spitfire_flush_dtlb_nucleus_page(unsigned long page)
: "r" (page | 0x20), "i" (ASI_DMMU_DEMAP));
}
-static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
+static inline void spitfire_flush_itlb_nucleus_page(unsigned long page)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
@@ -172,7 +171,7 @@ static __inline__ void spitfire_flush_itlb_nucleus_page(unsigned long page)
}
/* Cheetah has "all non-locked" tlb flushes. */
-static __inline__ void cheetah_flush_dtlb_all(void)
+static inline void cheetah_flush_dtlb_all(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
@@ -180,7 +179,7 @@ static __inline__ void cheetah_flush_dtlb_all(void)
: "r" (0x80), "i" (ASI_DMMU_DEMAP));
}
-static __inline__ void cheetah_flush_itlb_all(void)
+static inline void cheetah_flush_itlb_all(void)
{
__asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
"membar #Sync"
@@ -202,7 +201,7 @@ static __inline__ void cheetah_flush_itlb_all(void)
* ASI_{D,I}TLB_DATA_ACCESS loads, doing the load twice fixes
* the problem for me. -DaveM
*/
-static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
+static inline unsigned long cheetah_get_ldtlb_data(int entry)
{
unsigned long data;
@@ -215,7 +214,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_data(int entry)
return data;
}
-static __inline__ unsigned long cheetah_get_litlb_data(int entry)
+static inline unsigned long cheetah_get_litlb_data(int entry)
{
unsigned long data;
@@ -228,7 +227,7 @@ static __inline__ unsigned long cheetah_get_litlb_data(int entry)
return data;
}
-static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
+static inline unsigned long cheetah_get_ldtlb_tag(int entry)
{
unsigned long tag;
@@ -240,7 +239,7 @@ static __inline__ unsigned long cheetah_get_ldtlb_tag(int entry)
return tag;
}
-static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
+static inline unsigned long cheetah_get_litlb_tag(int entry)
{
unsigned long tag;
@@ -252,7 +251,7 @@ static __inline__ unsigned long cheetah_get_litlb_tag(int entry)
return tag;
}
-static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
+static inline void cheetah_put_ldtlb_data(int entry, unsigned long data)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -262,7 +261,7 @@ static __inline__ void cheetah_put_ldtlb_data(int entry, unsigned long data)
"i" (ASI_DTLB_DATA_ACCESS));
}
-static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
+static inline void cheetah_put_litlb_data(int entry, unsigned long data)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -272,7 +271,7 @@ static __inline__ void cheetah_put_litlb_data(int entry, unsigned long data)
"i" (ASI_ITLB_DATA_ACCESS));
}
-static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
+static inline unsigned long cheetah_get_dtlb_data(int entry, int tlb)
{
unsigned long data;
@@ -284,7 +283,7 @@ static __inline__ unsigned long cheetah_get_dtlb_data(int entry, int tlb)
return data;
}
-static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
+static inline unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
{
unsigned long tag;
@@ -294,7 +293,7 @@ static __inline__ unsigned long cheetah_get_dtlb_tag(int entry, int tlb)
return tag;
}
-static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
+static inline void cheetah_put_dtlb_data(int entry, unsigned long data, int tlb)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"
@@ -304,7 +303,7 @@ static __inline__ void cheetah_put_dtlb_data(int entry, unsigned long data, int
"i" (ASI_DTLB_DATA_ACCESS));
}
-static __inline__ unsigned long cheetah_get_itlb_data(int entry)
+static inline unsigned long cheetah_get_itlb_data(int entry)
{
unsigned long data;
@@ -317,7 +316,7 @@ static __inline__ unsigned long cheetah_get_itlb_data(int entry)
return data;
}
-static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
+static inline unsigned long cheetah_get_itlb_tag(int entry)
{
unsigned long tag;
@@ -327,7 +326,7 @@ static __inline__ unsigned long cheetah_get_itlb_tag(int entry)
return tag;
}
-static __inline__ void cheetah_put_itlb_data(int entry, unsigned long data)
+static inline void cheetah_put_itlb_data(int entry, unsigned long data)
{
__asm__ __volatile__("stxa %0, [%1] %2\n\t"
"membar #Sync"