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author | H. Peter Anvin <hpa@zytor.com> | 2008-09-04 08:08:42 -0700 |
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committer | H. Peter Anvin <hpa@zytor.com> | 2008-09-04 08:08:42 -0700 |
commit | 7203781c98ad9147564d327de6f6513ad8fc0f4e (patch) | |
tree | 5c29a2a04a626bf08a0d56fd8a0068b3c92ad284 /include/asm-x86/processor.h | |
parent | 671eef85a3e885dff4ce210d8774ad50a91d5967 (diff) | |
parent | af2e1f276ff08f17192411ea3b71c13a758dfe12 (diff) |
Merge branch 'x86/cpu' into x86/core
Conflicts:
arch/x86/kernel/cpu/feature_names.c
include/asm-x86/cpufeature.h
Diffstat (limited to 'include/asm-x86/processor.h')
-rw-r--r-- | include/asm-x86/processor.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h index 6d5648945ebf..10471cfab145 100644 --- a/include/asm-x86/processor.h +++ b/include/asm-x86/processor.h @@ -732,6 +732,29 @@ extern unsigned long boot_option_idle_override; extern unsigned long idle_halt; extern unsigned long idle_nomwait; +/* + * on systems with caches, caches must be flashed as the absolute + * last instruction before going into a suspended halt. Otherwise, + * dirty data can linger in the cache and become stale on resume, + * leading to strange errors. + * + * perform a variety of operations to guarantee that the compiler + * will not reorder instructions. wbinvd itself is serializing + * so the processor will not reorder. + * + * Systems without cache can just go into halt. + */ +static inline void wbinvd_halt(void) +{ + mb(); + /* check for clflush to determine if wbinvd is legal */ + if (cpu_has_clflush) + asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory"); + else + while (1) + halt(); +} + extern void enable_sep_cpu(void); extern int sysenter_setup(void); |