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authorShawn Guo <shawn.guo@freescale.com>2014-09-15 16:07:04 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-01-15 21:17:33 -0600
commit6e1cf2d6ef0d2025f824d8905a1594d9c46dc4de (patch)
tree656461d2d03679961fe95c0f0807519989809075 /include/dt-bindings
parentb79f29b6a77d82817bb501495ca49d051723a3be (diff)
ENGR00318063-2: ARM: imx6q: fix axi_sels mux setting
The current imx6q clock driver combines two mux clocks axi_alt_sel and axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a glitchless one. Fix it to match the clock tree in Reference Manual. shawn.guo: cherry-pick commit 973abca21604 from imx_3.10.y Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index a730f8b2c827..dd3a82a63784 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -253,6 +253,7 @@
#define IMX6QDL_PLL5_BYPASS 242
#define IMX6QDL_PLL6_BYPASS 243
#define IMX6QDL_PLL7_BYPASS 244
-#define IMX6QDL_CLK_END 245
+#define IMX6QDL_CLK_AXI_ALT_SEL 245
+#define IMX6QDL_CLK_END 246
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */