diff options
| author | Dong Aisheng <aisheng.dong@nxp.com> | 2019-12-02 18:02:25 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-12-02 18:02:25 +0800 |
| commit | 3e8c4bdbf7919947566636e4b8738f712ebd5322 (patch) | |
| tree | 5aa144c8a7c52f6c4dca5c7458175cc438f4f63f /include/dt-bindings | |
| parent | dbdab14cb09df1e96010b9863c5da3a0cc56e63a (diff) | |
| parent | 79a2871019d2590882af2e7852de4a079b733650 (diff) | |
Merge branch 'dts/next' into next
* dts/next: (765 commits)
arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the Felix CPU port
arm64: dts: fsl: ls1028a: Specify that the Felix port 4 runs at 2.5Gbps
arm64: dts: fsl: Drop "compatible" string from Felix switch
arm64: dts: fsl: Specify phy-mode for CPU ports
LF-261: arm64: dts: imx8mq: Set parent clock for IMX8MQ_CLK_AUDIO_AHB
...
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/input/input.h | 3 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pads-imx8qxp.h | 24 |
2 files changed, 27 insertions, 0 deletions
diff --git a/include/dt-bindings/input/input.h b/include/dt-bindings/input/input.h index bcf0ae100f21..221253480b21 100644 --- a/include/dt-bindings/input/input.h +++ b/include/dt-bindings/input/input.h @@ -15,4 +15,7 @@ #define MATRIX_KEY(row, col, code) \ ((((row) & 0xFF) << 24) | (((col) & 0xFF) << 16) | ((code) & 0xFFFF)) +#define FT5416 0x54160002 +#define FT5426 0x54260002 + #endif /* _DT_BINDINGS_INPUT_INPUT_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qxp.h b/include/dt-bindings/pinctrl/pads-imx8qxp.h index fbfee7ecf844..bfe9ab7c684c 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qxp.h +++ b/include/dt-bindings/pinctrl/pads-imx8qxp.h @@ -748,4 +748,28 @@ #define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2 #define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4 +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +/*@}*/ + #endif /* _IMX8QXP_PADS_H */ |