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authorShengjiu Wang <shengjiu.wang@freescale.com>2014-09-05 19:21:04 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-01-15 21:17:16 -0600
commit3715474215cb2809cf6f330e1e060f63ecae2db6 (patch)
tree8fd90291ce6b7a168e49954c7858fef7971a93c4 /include/dt-bindings
parent4000b59333a097867ccc98054e97fabc7950ef8e (diff)
ARM: clk-imx6sl: refine clock tree for SSI
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> (cherry picked from commit 3f87323170408418f1c8d298c7152eb15e40fbf1)
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/imx6sl-clock.h8
1 files changed, 6 insertions, 2 deletions
diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h
index 2d909ce906c9..43c6a909b913 100644
--- a/include/dt-bindings/clock/imx6sl-clock.h
+++ b/include/dt-bindings/clock/imx6sl-clock.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2013 Freescale Semiconductor, Inc.
+ * Copyright 2013-2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -170,6 +170,10 @@
#define IMX6SL_PLL5_BYPASS 157
#define IMX6SL_PLL6_BYPASS 158
#define IMX6SL_PLL7_BYPASS 159
-#define IMX6SL_CLK_END 160
+#define IMX6SL_CLK_SSI1_IPG 160
+#define IMX6SL_CLK_SSI2_IPG 161
+#define IMX6SL_CLK_SSI3_IPG 162
+#define IMX6SL_CLK_END 163
+
#endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */