diff options
| author | Michael Turquette <mturquette@linaro.org> | 2015-01-27 16:26:12 -0800 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-01-27 16:26:12 -0800 |
| commit | b80418f3c05061094c57ad7a661c9fb14e3f8b73 (patch) | |
| tree | dd5d12e53b34f610a6f668504fe8ffb9ca063d3f /include/dt-bindings | |
| parent | e387088a03a07583f248a237cb00c5c955a394c9 (diff) | |
| parent | e142a4e91443d0fc2185c821626e66729f323d1c (diff) | |
Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.
Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/rk3288-cru.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index f60ce72a2b2c..1e626335acf3 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -80,6 +80,9 @@ #define SCLK_SDIO0_SAMPLE 119 #define SCLK_SDIO1_SAMPLE 120 #define SCLK_EMMC_SAMPLE 121 +#define SCLK_USBPHY480M_SRC 122 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 #define DCLK_VOP0 190 #define DCLK_VOP1 191 @@ -154,6 +157,7 @@ #define PCLK_PUBL0 365 #define PCLK_DDRUPCTL1 366 #define PCLK_PUBL1 367 +#define PCLK_WDT 368 /* hclk gates */ #define HCLK_GPS 448 |