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authorPadmavathi Venna <padma.v@samsung.com>2015-01-13 16:57:40 +0530
committerSylwester Nawrocki <s.nawrocki@samsung.com>2015-01-15 15:11:40 +0100
commit9cc2a0c95ff3f815deeba1ccd0d11b1d3bc46551 (patch)
tree554a4e642438b0ccdeff9f7b4e0b9708083afb78 /include/dt-bindings
parent83f191a7cdf5286a8f3745e847f50c29fa349da9 (diff)
clk: samsung: exynos7: add gate clock for DMA block
Add support for PDMA0 and PDMA1 gate clks. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'include/dt-bindings')
-rw-r--r--include/dt-bindings/clock/exynos7-clk.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index e33d0ca4c123..05e2a47bcb96 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -91,7 +91,9 @@
#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER 6
#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER 7
#define OSCCLK_PHY_CLKOUT_USB30_PHY 8
-#define FSYS0_NR_CLK 9
+#define ACLK_PDMA0 9
+#define ACLK_PDMA1 10
+#define FSYS0_NR_CLK 11
/* FSYS1 */
#define ACLK_MMC1 1