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authorKevin Cernekee <cernekee@gmail.com>2014-11-06 22:44:19 -0800
committerJason Cooper <jason@lakedaemon.net>2014-11-09 04:02:00 +0000
commitb79055952badbd73710685643bab44104f2509ea (patch)
treec079abc538b1a269c55a7941ca59ab3a942daa1a /include/linux/irq.h
parent2b28037632b1e62b92c0616f08652d806008c80d (diff)
genirq: Generic chip: Add big endian I/O accessors
Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating the irqchip. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Acked-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/1415342669-30640-5-git-send-email-cernekee@gmail.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Diffstat (limited to 'include/linux/irq.h')
-rw-r--r--include/linux/irq.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 0fecd95ba271..8588e5efe577 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -738,12 +738,14 @@ struct irq_chip_generic {
* the parent irq. Usually GPIO implementations
* @IRQ_GC_MASK_CACHE_PER_TYPE: Mask cache is chip type private
* @IRQ_GC_NO_MASK: Do not calculate irq_data->mask
+ * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
*/
enum irq_gc_flags {
IRQ_GC_INIT_MASK_CACHE = 1 << 0,
IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
IRQ_GC_NO_MASK = 1 << 3,
+ IRQ_GC_BE_IO = 1 << 4,
};
/*