Merge branch 'l4t/l4t-r16-r2' into colibri

Conflicts:
	arch/arm/mach-tegra/tegra3_usb_phy.c
	arch/arm/mach-tegra/usb_phy.c
	drivers/usb/gadget/tegra_udc.c
	drivers/usb/otg/Makefile
	drivers/video/tegra/fb.c
	sound/soc/tegra/tegra_pcm.c

5 files changed, 706 insertions, 22 deletions

diff --git a/include/linux/mfd/max77665.h b/include/linux/mfd/max77665.h
new file mode 100644
index 000000000000..380a1a4aac0d
--- /dev/null
+++ b/include/linux/mfd/max77665.h
@@ -0,0 +1,92 @@
+/*
+ * Core driver interface for MAXIM77665
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_MFD_MAX77665_H
+#define __LINUX_MFD_MAX77665_H
+
+#include <linux/irq.h>
+#include <linux/regmap.h>
+
+/* MAX77665 Interrups */
+enum {
+	MAX77665_IRQ_CHARGER,
+	MAX77665_IRQ_TOP_SYS,
+	MAX77665_IRQ_FLASH,
+	MAX77665_IRQ_MUIC,
+};
+
+enum {
+	MAX77665_I2C_SLAVE_PMIC,
+	MAX77665_I2C_SLAVE_MUIC,
+	MAX77665_I2C_SLAVE_HAPTIC,
+	MAX77665_I2C_SLAVE_MAX,
+};
+
+struct max77665 {
+	struct device		*dev;
+	struct i2c_client	*client[MAX77665_I2C_SLAVE_MAX];
+	struct regmap		*regmap[MAX77665_I2C_SLAVE_MAX];
+	struct irq_chip		irq_chip;
+	struct mutex		irq_lock;
+	int			irq_base;
+};
+
+struct max77665_platform_data {
+	int irq_base;
+};
+
+static inline int max77665_write(struct device *dev, int slv_id,
+		int reg, uint8_t val)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+
+	return regmap_write(maxim->regmap[slv_id], reg, val);
+}
+
+static inline int max77665_read(struct device *dev, int slv_id,
+		int reg, uint8_t *val)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+	unsigned int temp_val;
+	int ret;
+
+	ret = regmap_read(maxim->regmap[slv_id], reg, &temp_val);
+	if (!ret)
+		*val = temp_val;
+	return ret;
+}
+
+static inline int max77665_set_bits(struct device *dev, int slv_id,
+		int reg, uint8_t bit_num)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+
+	return regmap_update_bits(maxim->regmap[slv_id],
+				reg, BIT(bit_num), ~0u);
+}
+
+static inline int max77665_clr_bits(struct device *dev, int slv_id,
+		int reg, uint8_t bit_num)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+
+	return regmap_update_bits(maxim->regmap[slv_id],
+				reg, BIT(bit_num), 0u);
+}
+
+#endif /*__LINUX_MFD_MAX77665_H */
diff --git a/include/linux/mfd/tlv320aic3262-core.h b/include/linux/mfd/tlv320aic3262-core.h
new file mode 100644
index 000000000000..3c79ae98f860
--- /dev/null
+++ b/include/linux/mfd/tlv320aic3262-core.h
@@ -0,0 +1,237 @@
+#ifndef __MFD_AIC3262_CORE_H__
+#define __MFD_AIC3262_CORE_H__
+
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+enum aic3262_type {
+	TLV320AIC3262 = 0,
+};
+
+#define AIC3262_IRQ_HEADSET_DETECT	0
+#define AIC3262_IRQ_BUTTON_PRESS	1
+#define AIC3262_IRQ_DAC_DRC		2
+#define AIC3262_IRQ_AGC_NOISE		3
+#define AIC3262_IRQ_OVER_CURRENT	4
+#define AIC3262_IRQ_OVERFLOW_EVENT	5
+#define AIC3262_IRQ_SPEAKER_OVER_TEMP	6
+
+#define AIC3262_GPIO1			7
+#define AIC3262_GPIO2			8
+#define AIC3262_GPI1			9
+#define AIC3262_GPI2			10
+#define AIC3262_GPO1			11
+
+union aic326x_reg_union {
+	struct aic326x_reg {
+		u8 offset;
+		u8 page;
+		u8 book;
+		u8 reserved;
+	} aic326x_register;
+	unsigned int aic326x_register_int;
+};
+
+/****************************             ************************************/
+
+/*
+ *****************************************************************************
+ * Structures Definitions
+ *****************************************************************************
+ */
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_setup_data |
+ *          i2c specific data setup for AIC3262.
+ * @field   unsigned short |i2c_address |
+ *          Unsigned short for i2c address.
+ *----------------------------------------------------------------------------
+ */
+struct aic3262_setup_data {
+	unsigned short i2c_address;
+};
+
+/* GPIO API */
+#define AIC3262_NUM_GPIO 5	/* include 2 GPI and 1 GPO pins */
+enum {
+	AIC3262_GPIO1_FUNC_DISABLED =		0,
+	AIC3262_GPIO1_FUNC_INPUT =		1,
+	AIC3262_GPIO1_FUNC_OUTPUT =		3,
+	AIC3262_GPIO1_FUNC_CLOCK_OUTPUT =	4,
+	AIC3262_GPIO1_FUNC_INT1_OUTPUT =	5,
+	AIC3262_GPIO1_FUNC_INT2_OUTPUT =	6,
+	AIC3262_GPIO1_FUNC_ADC_MOD_CLK_OUTPUT =	10,
+	AIC3262_GPIO1_FUNC_SAR_ADC_INTERRUPT =	12,
+	AIC3262_GPIO1_FUNC_ASI1_DATA_OUTPUT =	15,
+	AIC3262_GPIO1_FUNC_ASI1_WCLK =		16,
+	AIC3262_GPIO1_FUNC_ASI1_BCLK =		17,
+	AIC3262_GPIO1_FUNC_ASI2_WCLK =		18,
+	AIC3262_GPIO1_FUNC_ASI2_BCLK =		19,
+	AIC3262_GPIO1_FUNC_ASI3_WCLK =		20,
+	AIC3262_GPIO1_FUNC_ASI3_BCLK =		21
+};
+
+enum {
+	AIC3262_GPIO2_FUNC_DISABLED =		0,
+	AIC3262_GPIO2_FUNC_INPUT =		1,
+	AIC3262_GPIO2_FUNC_OUTPUT =		3,
+	AIC3262_GPIO2_FUNC_CLOCK_OUTPUT =	4,
+	AIC3262_GPIO2_FUNC_INT1_OUTPUT =	5,
+	AIC3262_GPIO2_FUNC_INT2_OUTPUT =	6,
+	AIC3262_GPIO2_FUNC_ADC_MOD_CLK_OUTPUT = 10,
+	AIC3262_GPIO2_FUNC_SAR_ADC_INTERRUPT =	12,
+	AIC3262_GPIO2_FUNC_ASI1_DATA_OUTPUT =	15,
+	AIC3262_GPIO2_FUNC_ASI1_WCLK =		16,
+	AIC3262_GPIO2_FUNC_ASI1_BCLK =		17,
+	AIC3262_GPIO2_FUNC_ASI2_WCLK =		18,
+	AIC3262_GPIO2_FUNC_ASI2_BCLK =		19,
+	AIC3262_GPIO2_FUNC_ASI3_WCLK =		20,
+	AIC3262_GPIO2_FUNC_ASI3_BCLK =		21
+};
+enum {
+	AIC3262_GPO1_FUNC_DISABLED =		0,
+	AIC3262_GPO1_FUNC_MSO_OUTPUT_FOR_SPI =	1,
+	AIC3262_GPO1_FUNC_GENERAL_PURPOSE_OUTPUT = 2,
+	AIC3262_GPO1_FUNC_CLOCK_OUTPUT =	3,
+	AIC3262_GPO1_FUNC_INT1_OUTPUT =	4,
+	AIC3262_GPO1_FUNC_INT2_OUTPUT =	5,
+	AIC3262_GPO1_FUNC_ADC_MOD_CLK_OUTPUT =	7,
+	AIC3262_GPO1_FUNC_SAR_ADC_INTERRUPT =	12,
+	AIC3262_GPO1_FUNC_ASI1_DATA_OUTPUT =	15,
+};
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_configs |
+ *          AIC3262 initialization data which has register offset and register
+ *          value.
+ * @field   u8 | book_no |
+ *          AIC3262 Book Number Offsets required for initialization..
+ * @field   u16 | reg_offset |
+ *          AIC3262 Register offsets required for initialization..
+ * @field   u8 | reg_val |
+ *          value to set the AIC3262 register to initialize the AIC3262.
+ *---------------------------------------------------------------------------
+ */
+struct aic3262_configs {
+	u8 book_no;
+	u16 reg_offset;
+	u8 reg_val;
+};
+
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_rate_divs |
+ *          Setting up the values to get different freqencies
+ *
+ * @field   u32 | mclk |
+ *          Master clock
+ * @field   u32 | rate |
+ *          sample rate
+ * @field   u8 | p_val |
+ *          value of p in PLL
+ * @field   u32 | pll_j |
+ *          value for pll_j
+ * @field   u32 | pll_d |
+ *          value for pll_d
+ * @field   u32 | dosr |
+ *          value to store dosr
+ * @field   u32 | ndac |
+ *          value for ndac
+ * @field   u32 | mdac |
+ *          value for mdac
+ * @field   u32 | aosr |
+ *          value for aosr
+ * @field   u32 | nadc |
+ *          value for nadc
+ * @field   u32 | madc |
+ *          value for madc
+ * @field   u32 | blck_N |
+ *          value for block N
+ */
+struct aic3262 {
+	struct mutex io_lock;
+	struct mutex irq_lock;
+	enum aic3262_type type;
+	struct device *dev;
+	int (*read_dev)(struct aic3262 *aic3262, unsigned int reg,
+			int bytes, void *dest);
+	int (*write_dev)(struct aic3262 *aic3262, unsigned int reg,
+			 int bytes, const void *src);
+
+	void *control_data;
+	unsigned int irq;
+	unsigned int irq_base;
+	u8 irq_masks_cur;
+	u8 irq_masks_cache;
+	/* Used over suspend/resume */
+	bool suspended;
+	u8 book_no;
+	u8 page_no;
+};
+
+struct aic3262_gpio_setup {
+	u8 used;		/* GPIO, GPI and GPO is used in the board, */
+				/* used = 1 else 0 */
+	u8 in;			/* GPIO is used as input, in = 1 else in = 0 */
+				/* GPI in = 1, GPO in = 0 */
+	unsigned int in_reg;	/* if GPIO is input,
+					register to write the mask. */
+	u8 in_reg_bitmask;	/* bitmask for 'value' to be
+					written into in_reg */
+	u8 in_reg_shift;	/* bits to shift to write 'value'
+					into in_reg */
+	u8 value;		/* value to be written
+					gpio_control_reg if GPIO */
+				/* is output, in_reg if its input */
+};
+
+struct aic3262_pdata {
+	unsigned int audio_mclk1;
+	unsigned int audio_mclk2;
+	unsigned int gpio_irq;	/* whether AIC3262 interrupts the host AP on */
+				/* a GPIO pin of AP */
+	unsigned int gpio_reset;/* is the codec being reset by a gpio*/
+				/* [host] pin, if yes provide the number. */
+	struct aic3262_gpio_setup *gpio;/* all gpio configuration */
+	int naudint_irq;	/* audio interrupt */
+	unsigned int irq_base;
+};
+
+static inline int aic3262_request_irq(struct aic3262 *aic3262, int irq,
+				      irq_handler_t handler,
+				      unsigned long irqflags, const char *name,
+				      void *data)
+{
+	if (!aic3262->irq_base)
+		return -EINVAL;
+
+	return request_threaded_irq(aic3262->irq_base + irq, NULL, handler,
+				    irqflags, name, data);
+}
+
+static inline int aic3262_free_irq(struct aic3262 *aic3262, int irq, void *data)
+{
+	if (!aic3262->irq_base)
+		return -EINVAL;
+
+	free_irq(aic3262->irq_base + irq, data);
+	return 0;
+}
+
+/* Device I/O API */
+int aic3262_reg_read(struct aic3262 *aic3262, unsigned int reg);
+int aic3262_reg_write(struct aic3262 *aic3262, unsigned int reg,
+		      unsigned char val);
+int aic3262_set_bits(struct aic3262 *aic3262, unsigned int reg,
+		     unsigned char mask, unsigned char val);
+int aic3262_bulk_read(struct aic3262 *aic3262, unsigned int reg,
+		      int count, u8 *buf);
+int aic3262_bulk_write(struct aic3262 *aic3262, unsigned int reg,
+		       int count, const u8 *buf);
+int aic3262_wait_bits(struct aic3262 *aic3262, unsigned int reg,
+		      unsigned char mask, unsigned char val, int delay,
+		      int counter);
+
+int aic3262_irq_init(struct aic3262 *aic3262);
+void aic3262_irq_exit(struct aic3262 *aic3262);
+
+#endif /* End of __MFD_AIC3262_CORE_H__ */
diff --git a/include/linux/mfd/tlv320aic3262-registers.h b/include/linux/mfd/tlv320aic3262-registers.h
new file mode 100644
index 000000000000..bdd7dfed80cd
--- /dev/null
+++ b/include/linux/mfd/tlv320aic3262-registers.h
@@ -0,0 +1,323 @@
+
+#ifndef __MFD_AIC3262_REGISTERS_H__
+#define __MFD_AIC3262_REGISTERS_H__
+
+#define MAKE_REG(book, page, offset) \
+	(unsigned int)((book << 16)|(page << 8)|offset)
+
+/* ****************** Book 0 Registers **************************************/
+
+/* ****************** Page 0 Registers **************************************/
+#define AIC3262_PAGE_SEL_REG		MAKE_REG(0, 0, 0)
+#define AIC3262_RESET_REG		MAKE_REG(0, 0, 1)
+#define AIC3262_REV_PG_ID		MAKE_REG(0, 0, 2)
+#define AIC3262_REV_MASK		(0b01110000)
+#define AIC3262_REV_SHIFT		4
+#define AIC3262_PG_MASK			(0b00000111)
+#define AIC3262_PG_SHIFT		0
+#define AIC3262_DAC_ADC_CLKIN_REG	MAKE_REG(0, 0, 4)
+#define AIC3262_PLL_CLKIN_REG		MAKE_REG(0, 0, 5)
+#define AIC3262_PLL_CLKIN_MASK		(0b00111100)
+#define AIC3262_PLL_CLKIN_SHIFT		2
+#define AIC3262_PLL_CLKIN_MCLK1		0
+#define AIC3262_PLL_CLKIN_BCLK1		1
+#define AIC3262_PLL_CLKIN_GPIO1		2
+#define AIC3262_PLL_CLKIN_DIN1		3
+#define AIC3262_PLL_CLKIN_BCLK2		4
+#define AIC3262_PLL_CLKIN_GPI1		5
+#define AIC3262_PLL_CLKIN_HF_REF_CLK	6
+#define AIC3262_PLL_CLKIN_GPIO2		7
+#define AIC3262_PLL_CLKIN_GPI2		8
+#define AIC3262_PLL_CLKIN_MCLK2		9
+#define AIC3262_CLK_VAL_MASK		0x7f
+#define AIC3262_PLL_CLK_RANGE_REG	MAKE_REG(0, 0, 5)
+#define AIC3262_PLL_PR_POW_REG		MAKE_REG(0, 0, 6)
+#define AIC3262_PLL_PVAL_MASK		0x70
+#define AIC3262_PLL_RVAL_MASK		0x0F
+
+#define AIC3262_ENABLE_CLK_MASK		0x80
+#define AIC3262_ENABLE_CLK		0x80
+
+#define AIC3262_PLL_J_REG		MAKE_REG(0, 0, 7)
+#define AIC3262_JVAL_MASK		0x3f
+#define AIC3262_PLL_D_MSB		MAKE_REG(0, 0, 8)
+#define AIC3262_DVAL_MSB_MASK		0xf
+#define AIC3262_DVAL_LSB_MASK		0xff
+#define AIC3262_PLL_D_LSB		MAKE_REG(0, 0, 9)
+#define AIC3262_PLL_CKIN_DIV		MAKE_REG(0, 0, 10)
+
+#define AIC3262_NDAC_DIV_POW_REG	MAKE_REG(0, 0, 11)
+#define AIC3262_MDAC_DIV_POW_REG	MAKE_REG(0, 0, 12)
+#define AIC3262_DOSR_MSB_REG		MAKE_REG(0, 0, 13)
+#define AIC3262_DOSR_MSB_MASK		0x3
+#define AIC3262_DOSR_LSB_REG		MAKE_REG(0, 0, 14)
+#define AIC3262_DOSR_LSB_MASK		0xFF
+
+#define AIC3262_NADC_DIV_POW_REG	MAKE_REG(0, 0, 18)
+#define AIC3262_MADC_DIV_POW_REG	MAKE_REG(0, 0, 19)
+#define AIC3262_AOSR_REG		MAKE_REG(0, 0, 20)
+#define AIC3262_CLKOUT_MUX		MAKE_REG(0, 0, 21)
+#define AIC3262_CLKOUT_MDIV_VAL		MAKE_REG(0, 0, 22)
+#define AIC3262_TIMER_REG		MAKE_REG(0, 0, 23)
+
+#define AIC3262_LF_CLK_CNTL		MAKE_REG(0, 0, 24)
+#define AIC3262_HF_CLK_CNTL_R1		MAKE_REG(0, 0, 25)
+#define AIC3262_HF_CLK_CNTL_R2		MAKE_REG(0, 0, 26)
+#define AIC3262_HF_CLK_CNTL_R3		MAKE_REG(0, 0, 27)
+#define AIC3262_HF_CLK_CNTL_R4		MAKE_REG(0, 0, 28)
+#define AIC3262_HF_CLK_TRIM_R1		MAKE_REG(0, 0, 29)
+#define AIC3262_HF_CLK_TRIM_R2		MAKE_REG(0, 0, 30)
+#define AIC3262_HF_CLK_TRIM_R3		MAKE_REG(0, 0, 31)
+#define AIC3262_HF_CLK_TRIM_R4		MAKE_REG(0, 0, 32)
+#define AIC3262_LDAC_POWER_MASK		0x80
+#define AIC3262_RDAC_POWER_MASK		0x08
+#define AIC3262_DAC_POWER_MASK		0x88
+#define AIC3262_DAC_FLAG		MAKE_REG(0, 0, 37)
+#define AIC3262_LADC_POWER_MASK		0x40
+#define AIC3262_RADC_POWER_MASK		0x04
+#define AIC3262_ADC_POWER_MASK		0x44
+#define AIC3262_ADC_FLAG                MAKE_REG(0, 0, 36)
+#define AIC3262_JACK_WITH_STEREO_HS	(0b00000010)
+#define AIC3262_JACK_WITH_MIC		(0b00110000)
+#define AIC3262_HEADSET_NOT_INSERTED	(0b00000011)
+
+#define AIC3262_INT_STICKY_FLAG1		MAKE_REG(0, 0, 42)
+#define AIC3262_LEFT_DAC_OVERFLOW_INT	0x80
+#define AIC3262_RIGHT_DAC_OVERFLOW_INT	0x40
+#define AIC3262_MINIDSP_D_BARREL_SHIFT_OVERFLOW_INT	0x20
+#define AIC3262_LEFT_ADC_OVERFLOW_INT	0x08
+#define AIC3262_RIGHT_ADC_OVERFLOW_INT	0x04
+#define AIC3262_MINIDSP_A_BARREL_SHIFT_OVERFLOW_INT	0x02
+#define AIC3262_INT_STICKY_FLAG2		MAKE_REG(0, 0, 44)
+#define AIC3262_LEFT_OUTPUT_DRIVER_OVERCURRENT_INT	0x80
+#define AIC3262_RIGHT_OUTPUT_DRIVER_OVERCURRENT_INT	0x40
+#define AIC3262_BUTTON_PRESS_INT			0x20
+#define AIC3262_HEADSET_PLUG_UNPLUG_INT			0x10
+#define AIC3262_LEFT_DRC_THRES_INT			0x08
+#define AIC3262_RIGHT_DRC_THRES_INT			0x04
+#define AIC3262_MINIDSP_D_STD_INT			0x02
+#define AIC3262_RIGHT_DRC_AUX_INT			0x01
+#define AIC3262_INT_STICKY_FLAG3		MAKE_REG(0, 0, 45)
+#define AIC3262_SPK_OVER_CURRENT_INT		0x80
+#define AIC3262_LEFT_AGC_NOISE_INT			0x40
+#define AIC3262_RIGHT_AGC_NOISE_INT			0x20
+#define AIC3262_INT1_CNTL		MAKE_REG(0, 0, 48)
+#define AIC3262_HEADSET_IN_MASK		0x80
+#define AIC3262_BUTTON_PRESS_MASK	0x40
+#define AIC3262_DAC_DRC_THRES_MASK	0x20
+#define AIC3262_AGC_NOISE_MASK		0x10
+#define AIC3262_OVER_CURRENT_MASK	0x08
+#define AIC3262_OVERFLOW_MASK		0x04
+#define AIC3262_SPK_OVERCURRENT_MASK	0x02
+#define AIC3262_INT2_CNTL		MAKE_REG(0, 0, 49)
+#define AIC3262_INT_FMT			MAKE_REG(0, 0, 51)
+
+#define AIC3262_DAC_PRB			MAKE_REG(0, 0, 60)
+#define AIC3262_ADC_PRB			MAKE_REG(0, 0, 61)
+#define AIC3262_PASI_DAC_DP_SETUP	MAKE_REG(0, 0, 63)
+
+#define AIC3262_DAC_MVOL_CONF		MAKE_REG(0, 0, 64)
+#define AIC3262_DAC_LR_MUTE_MASK	0xc
+#define AIC3262_DAC_LR_MUTE		0xc
+
+#define AIC3262_DAC_LVOL		MAKE_REG(0, 0, 65)
+#define AIC3262_DAC_RVOL		MAKE_REG(0, 0, 66)
+#define AIC3262_HP_DETECT		MAKE_REG(0, 0, 67)
+#define AIC3262_DRC_CNTL_R1		MAKE_REG(0, 0, 68)
+#define AIC3262_DRC_CNTL_R2		MAKE_REG(0, 0, 69)
+#define AIC3262_DRC_CNTL_R3		MAKE_REG(0, 0, 70)
+#define AIC3262_BEEP_CNTL_R1		MAKE_REG(0, 0, 71)
+#define AIC3262_BEEP_CNTL_R2		MAKE_REG(0, 0, 72)
+
+#define AIC3262_ADC_CHANNEL_POW		MAKE_REG(0, 0, 81)
+#define AIC3262_ADC_FINE_GAIN		MAKE_REG(0, 0, 82)
+#define AIC3262_LADC_VOL		MAKE_REG(0, 0, 83)
+#define AIC3262_RADC_VOL		MAKE_REG(0, 0, 84)
+#define AIC3262_ADC_PHASE		MAKE_REG(0, 0, 85)
+
+#define AIC3262_LAGC_CNTL		MAKE_REG(0, 0, 86)
+#define AIC3262_LAGC_CNTL_R2		MAKE_REG(0, 0, 87)
+#define AIC3262_LAGC_CNTL_R3		MAKE_REG(0, 0, 88)
+#define AIC3262_LAGC_CNTL_R4		MAKE_REG(0, 0, 89)
+#define AIC3262_LAGC_CNTL_R5		MAKE_REG(0, 0, 90)
+#define AIC3262_LAGC_CNTL_R6		MAKE_REG(0, 0, 91)
+#define AIC3262_LAGC_CNTL_R7		MAKE_REG(0, 0, 92)
+#define AIC3262_LAGC_CNTL_R8		MAKE_REG(0, 0, 93)
+
+#define AIC3262_RAGC_CNTL		MAKE_REG(0, 0, 94)
+#define AIC3262_RAGC_CNTL_R2		MAKE_REG(0, 0, 95)
+#define AIC3262_RAGC_CNTL_R3		MAKE_REG(0, 0, 96)
+#define AIC3262_RAGC_CNTL_R4		MAKE_REG(0, 0, 97)
+#define AIC3262_RAGC_CNTL_R5		MAKE_REG(0, 0, 98)
+#define AIC3262_RAGC_CNTL_R6		MAKE_REG(0, 0, 99)
+#define AIC3262_RAGC_CNTL_R7		MAKE_REG(0, 0, 100)
+#define AIC3262_RAGC_CNTL_R8		MAKE_REG(0, 0, 101)
+#define AIC3262_MINIDSP_ACCESS_CTRL	MAKE_REG(0, 0, 121)
+/* ****************** Page 1 Registers **************************************/
+#define AIC3262_PAGE_1			128
+
+#define AIC3262_POWER_CONF		MAKE_REG(0, 1, 1)
+
+#define AIC3262_AVDD_TO_DVDD_MASK	(0b00001000)
+#define	AIC3262_AVDD_TO_DVDD		0x8
+#define AIC3262_EXT_ANALOG_SUPPLY_MASK	(0b00000100)
+#define	AIC3262_EXT_ANALOG_SUPPLY_OFF	0x4
+
+#define AIC3262_LDAC_PTM		MAKE_REG(0, 1, 3)
+#define AIC3262_RDAC_PTM		MAKE_REG(0, 1, 4)
+#define AIC3262_CM_REG			MAKE_REG(0, 1, 8)
+#define AIC3262_HP_CTL			MAKE_REG(0, 1, 9)
+#define AIC3262_HP_DEPOP		MAKE_REG(0, 1, 11)
+#define AIC3262_RECV_DEPOP		MAKE_REG(0, 1, 12)
+#define AIC3262_MA_CNTL			MAKE_REG(0, 1, 17)
+#define AIC3262_LADC_PGA_MAL_VOL	MAKE_REG(0, 1, 18)
+#define AIC3262_RADC_PGA_MAR_VOL	MAKE_REG(0, 1, 19)
+
+#define AIC3262_LINE_AMP_CNTL_R1	MAKE_REG(0, 1, 22)
+#define AIC3262_LINE_AMP_CNTL_R2	MAKE_REG(0, 1, 23)
+
+#define AIC3262_HP_AMP_CNTL_R1		MAKE_REG(0, 1, 27)
+#define AIC3262_HP_AMP_CNTL_R2		MAKE_REG(0, 1, 28)
+#define AIC3262_HP_AMP_CNTL_R3		MAKE_REG(0, 1, 29)
+
+#define AIC3262_HPL_VOL			MAKE_REG(0, 1, 31)
+#define AIC3262_HPR_VOL			MAKE_REG(0, 1, 32)
+#define AIC3262_INT1_SEL_L		MAKE_REG(0, 1, 34)
+#define AIC3262_CHARGE_PUMP_CNTL	MAKE_REG(0, 1, 35)
+#define AIC3262_RAMP_CNTL_R1		MAKE_REG(0, 1, 36)
+#define AIC3262_RAMP_CNTL_R2		MAKE_REG(0, 1, 37)
+#define AIC3262_IN1L_SEL_RM		MAKE_REG(0, 1, 38)
+#define AIC3262_IN1R_SEL_RM		MAKE_REG(0, 1, 39)
+#define AIC3262_REC_AMP_CNTL_R5		MAKE_REG(0, 1, 40)
+#define AIC3262_RAMPR_VOL		MAKE_REG(0, 1, 41)
+#define AIC3262_RAMP_TIME_CNTL		MAKE_REG(0, 1, 42)
+#define AIC3262_SPK_AMP_CNTL_R1		MAKE_REG(0, 1, 45)
+#define AIC3262_SPK_AMP_CNTL_R2		MAKE_REG(0, 1, 46)
+#define AIC3262_SPK_AMP_CNTL_R3		MAKE_REG(0, 1, 47)
+#define AIC3262_SPK_AMP_CNTL_R4		MAKE_REG(0, 1, 48)
+#define AIC3262_MIC_BIAS_CNTL		MAKE_REG(0, 1, 51)
+
+#define AIC3262_LMIC_PGA_PIN		MAKE_REG(0, 1, 52)
+#define AIC3262_LMIC_PGA_PM_IN4		MAKE_REG(0, 1, 53)
+#define AIC3262_LMIC_PGA_MIN		MAKE_REG(0, 1, 54)
+#define AIC3262_RMIC_PGA_PIN		MAKE_REG(0, 1, 55)
+#define AIC3262_RMIC_PGA_PM_IN4		MAKE_REG(0, 1, 56)
+#define AIC3262_RMIC_PGA_MIN		MAKE_REG(0, 1, 57)
+#define AIC3262_HP_FLAG		        MAKE_REG(0, 1, 66)
+#define AIC3262_SPKL_POWER_MASK		0x2
+#define AIC3262_SPKR_POWER_MASK		0x1
+#define AIC3262_HPL_POWER_MASK		0x20
+#define AIC3262_HPR_POWER_MASK		0x10
+/* MIC PGA Gain Registers */
+#define AIC3262_MICL_PGA		MAKE_REG(0, 1, 59)
+#define AIC3262_MICR_PGA		MAKE_REG(0, 1, 60)
+#define AIC3262_HEADSET_TUNING1_REG	MAKE_REG(0, 1, 119)
+#define AIC3262_HEADSET_DETECTOR_PULSE_MASK (0b11000000)
+#define AIC3262_HEADSET_DETECTOR_PULSE_RESET (0b10000000)
+#define AIC3262_MIC_PWR_DLY		MAKE_REG(0, 1, 121)
+#define AIC3262_REF_PWR_DLY		MAKE_REG(0, 1, 122)
+#define AIC3262_CHIP_REF_PWR_ON_MASK	0x4
+#define AIC3262_CHIP_REF_PWR_ON		0x4
+/* ****************** Page 4 Registers **************************************/
+#define AIC3262_PAGE_4			512
+#define AIC3262_ASI1_BUS_FMT		MAKE_REG(0, 4, 1)
+#define AIC3262_ASI_SELECTION_MASK	(0b11100000)
+#define AIC3262_ASI_DATA_WORD_LENGTH_MASK	(0b00011000)
+#define AIC3262_ASI_BCLK_N_MASK		(0b01111111)
+#define AIC3262_ASI1_LCH_OFFSET		MAKE_REG(0, 4, 2)
+#define AIC3262_ASI1_RCH_OFFSET		MAKE_REG(0, 4, 3)
+#define AIC3262_ASI1_CHNL_SETUP		MAKE_REG(0, 4, 4)
+#define AIC3262_ASI1_MULTI_CH_SETUP_R1	MAKE_REG(0, 4, 5)
+#define AIC3262_ASI1_MULTI_CH_SETUP_R2	MAKE_REG(0, 4, 6)
+#define AIC3262_ASI1_ADC_INPUT_CNTL	MAKE_REG(0, 4, 7)
+#define AIC3262_ASI1_DAC_OUT_CNTL	MAKE_REG(0, 4, 8)
+#define AIC3262_ASI1_ADC_OUT_TRISTATE	MAKE_REG(0, 4, 9)
+#define AIC3262_ASI1_BWCLK_CNTL_REG	MAKE_REG(0, 4, 10)
+#define AIC3262_ASI1_BCLK_N_CNTL	MAKE_REG(0, 4, 11)
+#define AIC3262_ASI1_BCLK_N		MAKE_REG(0, 4, 12)
+#define AIC3262_ASI1_WCLK_N		MAKE_REG(0, 4, 13)
+#define AIC3262_ASI1_BWCLK_OUT_CNTL	MAKE_REG(0, 4, 14)
+#define AIC3262_ASI1_DOUT_CNTL		MAKE_REG(0, 4, 15)
+#define AIC3262_ASI2_BUS_FMT	        MAKE_REG(0, 4, 17)
+#define AIC3262_ASI2_LCH_OFFSET		MAKE_REG(0, 4, 18)
+#define AIC3262_ASI2_ADC_INPUT_CNTL	MAKE_REG(0, 4, 23)
+#define AIC3262_ASI2_DAC_OUT_CNTL	MAKE_REG(0, 4, 24)
+#define AIC3262_ASI2_BWCLK_CNTL_REG	MAKE_REG(0, 4, 26)
+#define AIC3262_ASI2_BCLK_N_CNTL	MAKE_REG(0, 4, 27)
+#define AIC3262_ASI2_BCLK_N		MAKE_REG(0, 4, 28)
+#define AIC3262_ASI2_WCLK_N		MAKE_REG(0, 4, 29)
+#define AIC3262_ASI2_BWCLK_OUT_CNTL	MAKE_REG(0, 4, 30)
+#define AIC3262_ASI2_DOUT_CNTL		MAKE_REG(0, 4, 31)
+#define AIC3262_ASI3_BUS_FMT		MAKE_REG(0, 4, 33)
+#define AIC3262_ASI3_LCH_OFFSET		MAKE_REG(0, 4, 34)
+#define AIC3262_ASI3_ADC_INPUT_CNTL	MAKE_REG(0, 4, 39)
+#define AIC3262_ASI3_DAC_OUT_CNTL	MAKE_REG(0, 4, 40)
+#define AIC3262_ASI3_BWCLK_CNTL_REG	MAKE_REG(0, 4, 42)
+#define AIC3262_ASI3_BCLK_N_CNTL	MAKE_REG(0, 4, 43)
+#define AIC3262_ASI3_BCLK_N		MAKE_REG(0, 4, 44)
+#define AIC3262_ASI3_WCLK_N		MAKE_REG(0, 4, 45)
+#define AIC3262_ASI3_BWCLK_OUT_CNTL	MAKE_REG(0, 4, 46)
+#define AIC3262_ASI3_DOUT_CNTL		MAKE_REG(0, 4, 47)
+#define AIC3262_GPIO1_IO_CNTL		MAKE_REG(0, 4, 86)
+#define AIC3262_GPIO_D6_D2		(0b01111100)
+#define AIC3262_GPIO_D2_SHIFT		(2)
+#define AIC3262_GPIO_D1_SHIFT		(1)
+#define AIC3262_GPIO_D4_SHIFT		(4)
+#define AIC3262_GPIO2_IO_CNTL		MAKE_REG(0, 4, 87)
+#define AIC3262_GPI1_EN			MAKE_REG(0, 4, 91)
+#define AIC3262_GPI1_D2_D1		(0b00000110)
+#define AIC3262_GPI2_D5_D4		(0b00110000)
+#define AIC3262_GPI2_EN			MAKE_REG(0, 4, 92)
+#define AIC3262_GPO1_OUT_CNTL		MAKE_REG(0, 4, 96)
+#define AIC3262_GPO1_D4_D1		(0b00011110)
+#define AIC3262_DMIC_INPUT_CNTL		MAKE_REG(0, 4, 101)
+#define AIC3262_DMIC_CONFIGURE_MASK	(0b00011111)
+#define AIC3262_DMIC_CONFIGURE_SHIFT	(0)
+#define AIC3262_DMIC_GPI1_LEFT_GPI1_RIGHT	(0)
+#define AIC3262_DMIC_GPI2_LEFT_GPI2_RIGHT	(1)
+#define AIC3262_DMIC_DIN1_LEFT_DIN1_RIGHT	(2)
+#define AIC3262_DMIC_DIN2_LEFT_DIN2_RIGHT	(3)
+#define AIC3262_DMIC_GPI01_LEFT_GPI01_RIGHT	(4)
+#define AIC3262_DMIC_GPI02_LEFT_GPI02_RIGHT	(5)
+#define AIC3262_DMIC_MCLK2_LEFT_MCLK2_RIGHT	(6)
+#define AIC3262_DMIC_GPI1_LEFT_GPI2_RIGHT	(7)
+#define AIC3262_DMIC_GPI1_LEFT_DIN1_RIGHT	(8)
+#define AIC3262_DMIC_GPI1_LEFT_DIN2_RIGHT	(9)
+#define AIC3262_DMIC_GPI1_LEFT_GPIO1_RIGHT	(10)
+#define AIC3262_DMIC_GPI1_LEFT_GPIO2_RIGHT	(11)
+#define AIC3262_DMIC_GPI1_LEFT_MCLK2_RIGHT	(12)
+#define AIC3262_DMIC_GPI2_LEFT_DIN1_RIGHT	(13)
+#define AIC3262_DMIC_GPI2_LEFT_DIN2_RIGHT	(14)
+#define AIC3262_DMIC_GPI2_LEFT_GPIO1_RIGHT	(15)
+#define AIC3262_DMIC_GPI2_LEFT_GPIO2_RIGHT	(16)
+#define AIC3262_DMIC_GPI2_LEFT_MCLK2_RIGHT	(17)
+#define AIC3262_DMIC_DIN1_LEFT_DIN2_RIGHT	(18)
+#define AIC3262_DMIC_DIN1_LEFT_GPIO1_RIGHT	(19)
+#define AIC3262_DMIC_DIN1_LEFT_GPIO2_RIGHT	(20)
+#define AIC3262_DMIC_DIN1_LEFT_MCLK2_RIGHT	(21)
+#define AIC3262_DMIC_DIN2_LEFT_GPIO1_RIGHT	(22)
+#define AIC3262_DMIC_DIN2_LEFT_GPIO2_RIGHT	(23)
+#define AIC3262_DMIC_DIN2_LEFT_MCLK2_RIGHT	(24)
+#define AIC3262_DMIC_GPI01_LEFT_GPI02_RIGHT	(25)
+#define AIC3262_DMIC_GPI01_LEFT_MCLK2_RIGHT	(26)
+#define AIC3262_DMIC_GPI02_LEFT_MCLK2_RIGHT	(27)
+#define AIC3262_MINIDSP_DATA_PORT_CNTL	MAKE_REG(0, 4, 118)
+
+#define AIC3262_DAC_ASI_LR_UNMUTE_MASK	0x50
+#define AIC3262_DAC_ASI_LR_UNMUTE	0x50
+#define AIC3262_WCLK_BCLK_MASTER_MASK (0b00100110)
+#define AIC3262_WCLK_MASTER_MASK (0b00100000)
+#define AIC3262_BCLK_MASTER_MASK (0b00000100)
+#define AIC3262_BCLK_OFFSET_MASK (0b11111111)
+#define AIC3262_ASI_INTERFACE_MASK (0b11100000)
+#define AIC3262_WCLK_OUT_MASK (0b00100000)
+#define AIC3262_BCLK_OUT_MASK (0b00000100)
+#define AIC3262_BCLK_INV_MASK (0b00000010)
+
+#define AIC3262_ADC_ADAPTIVE_CRAM_REG    MAKE_REG(40, 0, 1)
+#define AIC3262_DAC_ADAPTIVE_BANK1_REG   MAKE_REG(80, 0, 1)
+#define AIC3262_DAC_ADAPTIVE_BANK2_REG   MAKE_REG(82, 0, 1)
+#define AIC3262_ADC_DATAPATH_SETUP      MAKE_REG(0, 0, 81)
+#define AIC3262_DAC_DATAPATH_SETUP      MAKE_REG(0, 0, 63)
+
+#endif
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 511ced59ef1a..7ae86b956710 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -1,5 +1,4 @@
 /*
- * include/linux/mfd/tps65090.h
  * Core driver interface for TI TPS65090 PMIC family
  *
  * Copyright (C) 2012 NVIDIA Corporation
@@ -23,31 +22,60 @@
 #ifndef __LINUX_MFD_TPS65090_H
 #define __LINUX_MFD_TPS65090_H
 
-#include <linux/rtc.h>
+#include <linux/irq.h>
+#include <linux/regmap.h>
 
-struct tps65090_subdev_info {
-	int		id;
-	const char	*name;
-	void		*platform_data;
+struct tps65090 {
+	struct device		*dev;
+	struct regmap		*rmap;
+	struct irq_chip		irq_chip;
+	struct mutex		irq_lock;
+	int			irq_base;
 };
 
 struct tps65090_platform_data {
 	int irq_base;
-	int num_subdevs;
-	struct tps65090_subdev_info *subdevs;
+	struct tps65090_regulator_platform_data **reg_pdata;
+	int num_reg_pdata;
 };
 
 /*
  * NOTE: the functions below are not intended for use outside
  * of the TPS65090 sub-device drivers
  */
-extern int tps65090_write(struct device *dev, int reg, uint8_t val);
-extern int tps65090_writes(struct device *dev, int reg, int len, uint8_t *val);
-extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
-extern int tps65090_reads(struct device *dev, int reg, int len, uint8_t *val);
-extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
-extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
-extern int tps65090_update(struct device *dev, int reg, uint8_t val,
-			   uint8_t bit_num);
+static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+
+	return regmap_write(tps->rmap, reg, val);
+}
+
+static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+	unsigned int temp_val;
+	int ret;
+
+	ret = regmap_read(tps->rmap, reg, &temp_val);
+	if (!ret)
+		*val = temp_val;
+	return ret;
+}
+
+static inline int tps65090_set_bits(struct device *dev, int reg,
+		uint8_t bit_num)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+
+	return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
+}
+
+static inline int tps65090_clr_bits(struct device *dev, int reg,
+		uint8_t bit_num)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+
+	return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
+}
 
 #endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
index b3b9480ce596..2fa29e910ba2 100644
--- a/include/linux/mfd/tps80031.h
+++ b/include/linux/mfd/tps80031.h
@@ -184,9 +184,12 @@ struct tps80031_pupd_init_data {
 	int setting;
 };
 
+struct tps80031_bg_platform_data {
+	int irq_base;
+	int battery_present;
+};
+
 struct tps80031_platform_data {
-	int num_subdevs;
-	struct tps80031_subdev_info *subdevs;
 	int gpio_base;
 	int irq_base;
 	struct tps80031_32kclock_plat_data *clk32k_pdata;
@@ -197,12 +200,13 @@ struct tps80031_platform_data {
 	bool use_power_off;
 	struct tps80031_pupd_init_data *pupd_init_data;
 	int pupd_init_data_size;
+	struct tps80031_regulator_platform_data **regulator_pdata;
+	int num_regulator_pdata;
+	struct tps80031_rtc_platform_data *rtc_pdata;
+	struct tps80031_bg_platform_data *bg_pdata;
+	struct tps80031_charger_platform_data *battery_charger_pdata;
 };
 
-struct tps80031_bg_platform_data {
-	int irq_base;
-	int battery_present;
-};
 
 /*
  * NOTE: the functions below are not intended for use outside