diff options
author | Krzysztof Kozlowski <k.kozlowski.k@gmail.com> | 2015-07-15 21:59:53 +0900 |
---|---|---|
committer | Mark Brown <broonie@kernel.org> | 2015-07-16 21:39:30 +0100 |
commit | 309a3e00a511a233acb25eec567a4b11c99d016a (patch) | |
tree | 58e5f5ada4c558ddf481bb2845888ef01fa65c63 /include/linux/mfd | |
parent | cceb433a1e2930301b33c79016eff147eb555cea (diff) |
mfd/extcon: max77843: Rename defines to allow inclusion with max77693
Add MAX77843_MUIC prefix to some of the defines used in max77843 extcon
driver so the max77693-private.h can be included simultaneously with
max77843-private.h.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'include/linux/mfd')
-rw-r--r-- | include/linux/mfd/max77843-private.h | 154 |
1 files changed, 77 insertions, 77 deletions
diff --git a/include/linux/mfd/max77843-private.h b/include/linux/mfd/max77843-private.h index 0121d9440340..c19303b0ccfd 100644 --- a/include/linux/mfd/max77843-private.h +++ b/include/linux/mfd/max77843-private.h @@ -318,62 +318,62 @@ enum max77843_irq_muic { MAX77843_INTSRCMASK_SYS_MASK | MAX77843_INTSRCMASK_CHGR_MASK) /* MAX77843 STATUS register*/ -#define STATUS1_ADC_SHIFT 0 -#define STATUS1_ADCERROR_SHIFT 6 -#define STATUS1_ADC1K_SHIFT 7 -#define STATUS2_CHGTYP_SHIFT 0 -#define STATUS2_CHGDETRUN_SHIFT 3 -#define STATUS2_DCDTMR_SHIFT 4 -#define STATUS2_DXOVP_SHIFT 5 -#define STATUS2_VBVOLT_SHIFT 6 -#define STATUS3_VBADC_SHIFT 0 -#define STATUS3_VDNMON_SHIFT 4 -#define STATUS3_DNRES_SHIFT 5 -#define STATUS3_MPNACK_SHIFT 6 - -#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT) -#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(STATUS1_ADCERROR_SHIFT) -#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(STATUS1_ADC1K_SHIFT) -#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT) -#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(STATUS2_CHGDETRUN_SHIFT) -#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(STATUS2_DCDTMR_SHIFT) -#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(STATUS2_DXOVP_SHIFT) -#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(STATUS2_VBVOLT_SHIFT) -#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << STATUS3_VBADC_SHIFT) -#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(STATUS3_VDNMON_SHIFT) -#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(STATUS3_DNRES_SHIFT) -#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(STATUS3_MPNACK_SHIFT) +#define MAX77843_MUIC_STATUS1_ADC_SHIFT 0 +#define MAX77843_MUIC_STATUS1_ADCERROR_SHIFT 6 +#define MAX77843_MUIC_STATUS1_ADC1K_SHIFT 7 +#define MAX77843_MUIC_STATUS2_CHGTYP_SHIFT 0 +#define MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT 3 +#define MAX77843_MUIC_STATUS2_DCDTMR_SHIFT 4 +#define MAX77843_MUIC_STATUS2_DXOVP_SHIFT 5 +#define MAX77843_MUIC_STATUS2_VBVOLT_SHIFT 6 +#define MAX77843_MUIC_STATUS3_VBADC_SHIFT 0 +#define MAX77843_MUIC_STATUS3_VDNMON_SHIFT 4 +#define MAX77843_MUIC_STATUS3_DNRES_SHIFT 5 +#define MAX77843_MUIC_STATUS3_MPNACK_SHIFT 6 + +#define MAX77843_MUIC_STATUS1_ADC_MASK (0x1f << MAX77843_MUIC_STATUS1_ADC_SHIFT) +#define MAX77843_MUIC_STATUS1_ADCERROR_MASK BIT(MAX77843_MUIC_STATUS1_ADCERROR_SHIFT) +#define MAX77843_MUIC_STATUS1_ADC1K_MASK BIT(MAX77843_MUIC_STATUS1_ADC1K_SHIFT) +#define MAX77843_MUIC_STATUS2_CHGTYP_MASK (0x7 << MAX77843_MUIC_STATUS2_CHGTYP_SHIFT) +#define MAX77843_MUIC_STATUS2_CHGDETRUN_MASK BIT(MAX77843_MUIC_STATUS2_CHGDETRUN_SHIFT) +#define MAX77843_MUIC_STATUS2_DCDTMR_MASK BIT(MAX77843_MUIC_STATUS2_DCDTMR_SHIFT) +#define MAX77843_MUIC_STATUS2_DXOVP_MASK BIT(MAX77843_MUIC_STATUS2_DXOVP_SHIFT) +#define MAX77843_MUIC_STATUS2_VBVOLT_MASK BIT(MAX77843_MUIC_STATUS2_VBVOLT_SHIFT) +#define MAX77843_MUIC_STATUS3_VBADC_MASK (0xf << MAX77843_MUIC_STATUS3_VBADC_SHIFT) +#define MAX77843_MUIC_STATUS3_VDNMON_MASK BIT(MAX77843_MUIC_STATUS3_VDNMON_SHIFT) +#define MAX77843_MUIC_STATUS3_DNRES_MASK BIT(MAX77843_MUIC_STATUS3_DNRES_SHIFT) +#define MAX77843_MUIC_STATUS3_MPNACK_MASK BIT(MAX77843_MUIC_STATUS3_MPNACK_SHIFT) /* MAX77843 CONTROL register */ -#define CONTROL1_COMP1SW_SHIFT 0 -#define CONTROL1_COMP2SW_SHIFT 3 -#define CONTROL1_IDBEN_SHIFT 7 -#define CONTROL2_LOWPWR_SHIFT 0 -#define CONTROL2_ADCEN_SHIFT 1 -#define CONTROL2_CPEN_SHIFT 2 -#define CONTROL2_ACC_DET_SHIFT 5 -#define CONTROL2_USBCPINT_SHIFT 6 -#define CONTROL2_RCPS_SHIFT 7 -#define CONTROL3_JIGSET_SHIFT 0 -#define CONTROL4_ADCDBSET_SHIFT 0 -#define CONTROL4_USBAUTO_SHIFT 4 -#define CONTROL4_FCTAUTO_SHIFT 5 -#define CONTROL4_ADCMODE_SHIFT 6 - -#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << CONTROL1_COMP1SW_SHIFT) -#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << CONTROL1_COMP2SW_SHIFT) -#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(CONTROL1_IDBEN_SHIFT) -#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(CONTROL2_LOWPWR_SHIFT) -#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(CONTROL2_ADCEN_SHIFT) -#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(CONTROL2_CPEN_SHIFT) -#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(CONTROL2_ACC_DET_SHIFT) -#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(CONTROL2_USBCPINT_SHIFT) -#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(CONTROL2_RCPS_SHIFT) -#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT) -#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << CONTROL4_ADCDBSET_SHIFT) -#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(CONTROL4_USBAUTO_SHIFT) -#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(CONTROL4_FCTAUTO_SHIFT) -#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << CONTROL4_ADCMODE_SHIFT) +#define MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT 0 +#define MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT 3 +#define MAX77843_MUIC_CONTROL1_IDBEN_SHIFT 7 +#define MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT 0 +#define MAX77843_MUIC_CONTROL2_ADCEN_SHIFT 1 +#define MAX77843_MUIC_CONTROL2_CPEN_SHIFT 2 +#define MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT 5 +#define MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT 6 +#define MAX77843_MUIC_CONTROL2_RCPS_SHIFT 7 +#define MAX77843_MUIC_CONTROL3_JIGSET_SHIFT 0 +#define MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT 0 +#define MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT 4 +#define MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT 5 +#define MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT 6 + +#define MAX77843_MUIC_CONTROL1_COMP1SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT) +#define MAX77843_MUIC_CONTROL1_COMP2SW_MASK (0x7 << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT) +#define MAX77843_MUIC_CONTROL1_IDBEN_MASK BIT(MAX77843_MUIC_CONTROL1_IDBEN_SHIFT) +#define MAX77843_MUIC_CONTROL2_LOWPWR_MASK BIT(MAX77843_MUIC_CONTROL2_LOWPWR_SHIFT) +#define MAX77843_MUIC_CONTROL2_ADCEN_MASK BIT(MAX77843_MUIC_CONTROL2_ADCEN_SHIFT) +#define MAX77843_MUIC_CONTROL2_CPEN_MASK BIT(MAX77843_MUIC_CONTROL2_CPEN_SHIFT) +#define MAX77843_MUIC_CONTROL2_ACC_DET_MASK BIT(MAX77843_MUIC_CONTROL2_ACC_DET_SHIFT) +#define MAX77843_MUIC_CONTROL2_USBCPINT_MASK BIT(MAX77843_MUIC_CONTROL2_USBCPINT_SHIFT) +#define MAX77843_MUIC_CONTROL2_RCPS_MASK BIT(MAX77843_MUIC_CONTROL2_RCPS_SHIFT) +#define MAX77843_MUIC_CONTROL3_JIGSET_MASK (0x3 << MAX77843_MUIC_CONTROL3_JIGSET_SHIFT) +#define MAX77843_MUIC_CONTROL4_ADCDBSET_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCDBSET_SHIFT) +#define MAX77843_MUIC_CONTROL4_USBAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) +#define MAX77843_MUIC_CONTROL4_FCTAUTO_MASK BIT(MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT) +#define MAX77843_MUIC_CONTROL4_ADCMODE_MASK (0x3 << MAX77843_MUIC_CONTROL4_ADCMODE_SHIFT) /* MAX77843 switch port */ #define COM_OPEN 0 @@ -383,38 +383,38 @@ enum max77843_irq_muic { #define COM_AUX_USB 4 #define COM_AUX_UART 5 -#define CONTROL1_COM_SW \ +#define MAX77843_MUIC_CONTROL1_COM_SW \ ((MAX77843_MUIC_CONTROL1_COMP1SW_MASK | \ MAX77843_MUIC_CONTROL1_COMP2SW_MASK)) -#define CONTROL1_SW_OPEN \ - ((COM_OPEN << CONTROL1_COMP1SW_SHIFT | \ - COM_OPEN << CONTROL1_COMP2SW_SHIFT)) -#define CONTROL1_SW_USB \ - ((COM_USB << CONTROL1_COMP1SW_SHIFT | \ - COM_USB << CONTROL1_COMP2SW_SHIFT)) -#define CONTROL1_SW_AUDIO \ - ((COM_AUDIO << CONTROL1_COMP1SW_SHIFT | \ - COM_AUDIO << CONTROL1_COMP2SW_SHIFT)) -#define CONTROL1_SW_UART \ - ((COM_UART << CONTROL1_COMP1SW_SHIFT | \ - COM_UART << CONTROL1_COMP2SW_SHIFT)) -#define CONTROL1_SW_AUX_USB \ - ((COM_AUX_USB << CONTROL1_COMP1SW_SHIFT | \ - COM_AUX_USB << CONTROL1_COMP2SW_SHIFT)) -#define CONTROL1_SW_AUX_UART \ - ((COM_AUX_UART << CONTROL1_COMP1SW_SHIFT | \ - COM_AUX_UART << CONTROL1_COMP2SW_SHIFT)) +#define MAX77843_MUIC_CONTROL1_SW_OPEN \ + ((COM_OPEN << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ + COM_OPEN << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) +#define MAX77843_MUIC_CONTROL1_SW_USB \ + ((COM_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ + COM_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) +#define MAX77843_MUIC_CONTROL1_SW_AUDIO \ + ((COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ + COM_AUDIO << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) +#define MAX77843_MUIC_CONTROL1_SW_UART \ + ((COM_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ + COM_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) +#define MAX77843_MUIC_CONTROL1_SW_AUX_USB \ + ((COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ + COM_AUX_USB << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) +#define MAX77843_MUIC_CONTROL1_SW_AUX_UART \ + ((COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP1SW_SHIFT | \ + COM_AUX_UART << MAX77843_MUIC_CONTROL1_COMP2SW_SHIFT)) #define MAX77843_DISABLE 0 #define MAX77843_ENABLE 1 #define CONTROL4_AUTO_DISABLE \ - ((MAX77843_DISABLE << CONTROL4_USBAUTO_SHIFT) | \ - (MAX77843_DISABLE << CONTROL4_FCTAUTO_SHIFT)) + ((MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \ + (MAX77843_DISABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)) #define CONTROL4_AUTO_ENABLE \ - ((MAX77843_ENABLE << CONTROL4_USBAUTO_SHIFT) | \ - (MAX77843_ENABLE << CONTROL4_FCTAUTO_SHIFT)) + ((MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_USBAUTO_SHIFT) | \ + (MAX77843_ENABLE << MAX77843_MUIC_CONTROL4_FCTAUTO_SHIFT)) /* MAX77843 SAFEOUT LDO Control register */ #define SAFEOUTCTRL_SAFEOUT1_SHIFT 0 |