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authorPavan Kunapuli <pkunapuli@nvidia.com>2013-10-24 19:03:45 +0530
committerBitan Biswas <bbiswas@nvidia.com>2013-10-29 06:29:37 -0700
commit08e714a85651abcb3cb332a4a9ec3c053d2b6b8d (patch)
treee4d4a9e21a098c3f47370c5e536096500813f018 /include/linux/mmc
parent05470edb23effa3823b29b97c1ba370f3603ca6b (diff)
mmc: host: sdhci: sdio delayed clock gate
Aggressive clock gate degrades sdio performance. Hence, sdio clock gate is delayed. - sdio clock gate is done if no further transaction starts within 20msec interval bug 1299485 Change-Id: Icb7a647bd4c725372173ea65894524f393220843 Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: http://git-master/r/304725 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'include/linux/mmc')
-rw-r--r--include/linux/mmc/sdhci.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index a689528dd28b..e4cb7de6d877 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -113,6 +113,8 @@ struct sdhci_host {
#define SDHCI_QUIRK2_SUPPORT_64BIT_DMA (1<<9)
/* Use 64 BIT addressing */
#define SDHCI_QUIRK2_USE_64BIT_ADDR (1<<10)
+/* sdio delayed clock gate */
+#define SDHCI_QUIRK2_SDIO_DELAYED_CLK_GATE (1<<11)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
@@ -200,6 +202,14 @@ struct sdhci_host {
bool edp_support;
struct sysedp_consumer *sysedpc;
+ struct delayed_work delayed_clk_gate_wrk;
+ bool sdio_clk_gate_init_done;
+ bool is_clk_on;
+
unsigned long private[0] ____cacheline_aligned;
};
+
+/* callback is registered during init */
+void delayed_clk_gate_cb(struct work_struct *work);
+
#endif /* LINUX_MMC_SDHCI_H */