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authorYu Zhao <yu.zhao@intel.com>2009-02-25 13:15:52 +0800
committerJesse Barnes <jbarnes@virtuousgeek.org>2009-03-20 10:48:08 -0700
commit998dd7c719f62dcfa91d7bf7f4eb9c160e03d817 (patch)
treed54f48be7101226b9843f941ae34cc6f8f330f8e /include/linux/pci_regs.h
parentc74d724462d1845535667f4d3f720e02e3432e53 (diff)
PCI: fix incorrect mask of PM No_Soft_Reset bit
Reviewed-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Yu Zhao <yu.zhao@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'include/linux/pci_regs.h')
-rw-r--r--include/linux/pci_regs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 027815b4635e..b647a4df59fc 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -235,7 +235,7 @@
#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
#define PCI_PM_CTRL 4 /* PM control and status register */
#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
-#define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
+#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */