diff options
| author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2011-11-21 21:33:18 -0800 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2011-11-24 17:15:23 +0900 |
| commit | 56242a1fc595d158eddefbb4d6d76e82c2535f55 (patch) | |
| tree | 78964e2ccde88e09ebb12412de26ab58f7b1417b /include/linux/sh_clk.h | |
| parent | a9098b372606a15745cdeb012de4ee91c0df82c4 (diff) | |
sh: clkfwk: setup clock parent from current register value
Some clocks can select its parent clock by CPG register.
But it might have been modified by boot-loader or something.
This patch removed fixed initial parent clock,
and setup it from their current register settings.
It works on div6 reparent clocks for now.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'include/linux/sh_clk.h')
| -rw-r--r-- | include/linux/sh_clk.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h index a20831cf336a..e834304c0b6a 100644 --- a/include/linux/sh_clk.h +++ b/include/linux/sh_clk.h @@ -131,10 +131,9 @@ int sh_clk_div4_enable_register(struct clk *clks, int nr, int sh_clk_div4_reparent_register(struct clk *clks, int nr, struct clk_div4_table *table); -#define SH_CLK_DIV6_EXT(_parent, _reg, _flags, _parents, \ +#define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ _num_parents, _src_shift, _src_width) \ { \ - .parent = _parent, \ .enable_reg = (void __iomem *)_reg, \ .flags = _flags, \ .parent_table = _parents, \ @@ -144,7 +143,11 @@ int sh_clk_div4_reparent_register(struct clk *clks, int nr, } #define SH_CLK_DIV6(_parent, _reg, _flags) \ - SH_CLK_DIV6_EXT(_parent, _reg, _flags, NULL, 0, 0, 0) +{ \ + .parent = _parent, \ + .enable_reg = (void __iomem *)_reg, \ + .flags = _flags, \ +} int sh_clk_div6_register(struct clk *clks, int nr); int sh_clk_div6_reparent_register(struct clk *clks, int nr); |