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authorStephen Warren <swarren@nvidia.com>2013-03-29 17:38:18 -0600
committerStephen Warren <swarren@nvidia.com>2013-03-29 18:10:22 -0600
commite4bcda28344cc4762c57ad7333f0472a39e83479 (patch)
tree7f9f74969ce073bb06e1da535bcf2ee6dcd97e40 /include/linux/tegra-powergate.h
parent7495b2eb0770b85e58af98b99faaf853e9563784 (diff)
ARM: tegra: move <mach/powergate.h> to <linux/tegra-powergate.h>
This is required so that code such as Tegra's PCIe and clock drivers can still access this header file once Tegra is converted to multiplatform, and <mach/> no longer exists. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'include/linux/tegra-powergate.h')
-rw-r--r--include/linux/tegra-powergate.h49
1 files changed, 49 insertions, 0 deletions
diff --git a/include/linux/tegra-powergate.h b/include/linux/tegra-powergate.h
new file mode 100644
index 000000000000..55c29a8d5015
--- /dev/null
+++ b/include/linux/tegra-powergate.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2010 Google, Inc
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_POWERGATE_H_
+#define _MACH_TEGRA_POWERGATE_H_
+
+struct clk;
+
+#define TEGRA_POWERGATE_CPU 0
+#define TEGRA_POWERGATE_3D 1
+#define TEGRA_POWERGATE_VENC 2
+#define TEGRA_POWERGATE_PCIE 3
+#define TEGRA_POWERGATE_VDEC 4
+#define TEGRA_POWERGATE_L2 5
+#define TEGRA_POWERGATE_MPE 6
+#define TEGRA_POWERGATE_HEG 7
+#define TEGRA_POWERGATE_SATA 8
+#define TEGRA_POWERGATE_CPU1 9
+#define TEGRA_POWERGATE_CPU2 10
+#define TEGRA_POWERGATE_CPU3 11
+#define TEGRA_POWERGATE_CELP 12
+#define TEGRA_POWERGATE_3D1 13
+
+#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
+#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
+
+int tegra_powergate_is_powered(int id);
+int tegra_powergate_power_on(int id);
+int tegra_powergate_power_off(int id);
+int tegra_powergate_remove_clamping(int id);
+
+/* Must be called with clk disabled, and returns with clk enabled */
+int tegra_powergate_sequence_power_up(int id, struct clk *clk);
+
+#endif /* _MACH_TEGRA_POWERGATE_H_ */