diff options
| author | Bai Ping <ping.bai@nxp.com> | 2017-10-30 16:27:02 +0800 |
|---|---|---|
| committer | Jason Liu <jason.hui.liu@nxp.com> | 2019-02-12 10:28:56 +0800 |
| commit | 60a2002f752404b5fc30b374bc71a3975902eb7a (patch) | |
| tree | 3cf24bfb63684d39a4dc59968ee79d6abfd362d0 /include/soc/imx | |
| parent | a3784a3abd6c4eb98b597dd717c208a2b40538cb (diff) | |
MLK-16689-03 driver: soc: Add busfreq driver for imx8mq
Add busfreq driver support on i.MX8MQ. The busfreq driver is
mainly used for dynamic DDR frequency change for power saving
feature. When there is no peripheral or DMA device has direct
access to DDR memory, we can lower the DDR frequency to save
power. Currently, we support frequency setpoint for LPDDR4:
(1): 3200mts, the DDRC core clock is sourced from 800MHz
dram_pll, the DDRC apb clock is 200MHz.
(2): 400mts, the DDRC core clock is source from sys1_pll_400m,
the DDRC apb clock is is sourced from sys1_pll_40m.
(3): 100mts, the DDRC core clock is sourced from sys1_pll_100m,
the DDRC apb clock is sourced from sys1_pll_40m.
In our busfreq driver, we have three mode supported:
* high bus mode <-----> 3200mts;
* audio bus mode <-----> 400mts;
* low bus mode <-----> 100mts;
The actual DDR frequency is done in ARM trusted firmware by calling
the SMCC SiP service call.
BuildInfo:
- IMX-MKIMAGE: 05d3d4a7d7, ATF: 724cc2b890
- SPL/Uboot: f72c10d2db;
Signed-off-by: Bai Ping <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'include/soc/imx')
| -rw-r--r-- | include/soc/imx/fsl_sip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/soc/imx/fsl_sip.h b/include/soc/imx/fsl_sip.h index 1f4e31933e0e..26481a0865ac 100644 --- a/include/soc/imx/fsl_sip.h +++ b/include/soc/imx/fsl_sip.h @@ -28,6 +28,8 @@ #define FSL_SIP_SRTC_PING_WDOG 0x04 #define FSL_SIP_SRTC_SET_TIMEOUT_WDOG 0x05 +#define FSL_SIP_DDR_DVFS 0xc2000004 + #define IMX8MQ_PD_MIPI 0 #define IMX8MQ_PD_PCIE1 1 #define IMX8MQ_PD_OTG1 2 |