diff options
| author | Liu Ying <victor.liu@nxp.com> | 2019-11-12 14:18:15 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 15:58:26 +0800 |
| commit | c735596b0629a56aafab64ac599ec44d8f084d61 (patch) | |
| tree | 7bbc048bfdb240422a7af93a5ca3dd6ffaeee119 /include/video | |
| parent | 3ecace49423ceb4c96b6a47d3681d4072d8a6a9c (diff) | |
gpu: imx: dpu: common: Add store9 support for sync mode fixup
Bit16 of store9's PIXENGCFG_STATIC register is used to control
the sync mode fixup logic implemented in store9. So, let's
add store9 support in the DPU core driver and export a function
for users to enable/disable the fixup logic.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Diffstat (limited to 'include/video')
| -rw-r--r-- | include/video/dpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/video/dpu.h b/include/video/dpu.h index 1cc5c8c5ccaf..96a53c7688bd 100644 --- a/include/video/dpu.h +++ b/include/video/dpu.h @@ -549,6 +549,12 @@ void layerblend_position(struct dpu_layerblend *lb, int x, int y); struct dpu_layerblend *dpu_lb_get(struct dpu_soc *dpu, int id); void dpu_lb_put(struct dpu_layerblend *lb); +/* Store Unit */ +struct dpu_store; +void store_pixengcfg_syncmode_fixup(struct dpu_store *st, bool enable); +struct dpu_store *dpu_st_get(struct dpu_soc *dpu, int id); +void dpu_st_put(struct dpu_store *st); + /* Timing Controller Unit */ struct dpu_tcon; int tcon_set_fmt(struct dpu_tcon *tcon, u32 bus_format); |