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authorTom Cherry <tcherry@nvidia.com>2012-03-20 16:59:51 -0700
committerSimone Willett <swillett@nvidia.com>2012-03-30 20:26:42 -0700
commitcbfacd822212e0bea2bd1a3430775d78ade66f5f (patch)
tree443d2077343ea10163bd9cb3daa4e7076e0543a7 /include/xen
parent62f9045abae25341107c9cfcfe2ef457c543a19e (diff)
arm: tegra: enterprise: use proper backlight clk_div for A03/A04tegra-l4t-r15-betategra-l4t-er-2012-04-02
The new TPS61160A part asks for the control PWM signal to be between 5kHZ and 100kHz. This change sets clk_div to 0x1D for a 5kHz signal. This change also installs a linear table for enterprise_bl_output_measured_a03. Bug 956246 Reviewed-on: http://git-master/r/91606 (cherry picked from commit 32a67cf7b1c8223abe8de7d88b4bcd1906cda0a2) Change-Id: Ic7907cfae6f918ef055add33615822ef8c5e0ec6 Signed-off-by: Tom Cherry <tcherry@nvidia.com> Reviewed-on: http://git-master/r/93051 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
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