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authorShengjiu Wang <shengjiu.wang@freescale.com>2014-08-08 15:02:47 +0800
committerNitin Garg <nitin.garg@freescale.com>2015-09-17 08:58:30 -0500
commit4fb28727545a587a79579ca50f24121436e8b10a (patch)
tree431321cd1ff339d7eb656ee64d584cf3affdc51e /include
parent400dd0d99f62cb7437572117e3de38e9afa4ec2c (diff)
ARM: clk-imx6q: refine clock tree for ESAI
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com> (cherry-picked from commit d140d15ae366a002140dc46b73c7bd22ebe16489)
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/clock/imx6qdl-clock.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index 0a009ad5d14d..c7b0fa8fe3e2 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -126,7 +126,7 @@
#define IMX6Q_CLK_ECSPI5 116
#define IMX6DL_CLK_I2C4 116
#define IMX6QDL_CLK_ENET 117
-#define IMX6QDL_CLK_ESAI 118
+#define IMX6QDL_CLK_ESAI_EXTAL 118
#define IMX6QDL_CLK_GPT_IPG 119
#define IMX6QDL_CLK_GPT_IPG_PER 120
#define IMX6QDL_CLK_GPU2D_CORE 121
@@ -216,7 +216,7 @@
#define IMX6QDL_CLK_LVDS2_SEL 205
#define IMX6QDL_CLK_LVDS1_GATE 206
#define IMX6QDL_CLK_LVDS2_GATE 207
-#define IMX6QDL_CLK_ESAI_AHB 208
+#define IMX6QDL_CLK_ESAI_MEM 208
#define IMX6QDL_CLK_LDB_DI0_DIV_7 209
#define IMX6QDL_CLK_LDB_DI1_DIV_7 210
#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 211
@@ -225,6 +225,7 @@
#define IMX6QDL_CLK_DCIC1 214
#define IMX6QDL_CLK_DCIC2 215
#define IMX6QDL_CLK_GPT_3M 216
-#define IMX6QDL_CLK_END 217
+#define IMX6QDL_CLK_ESAI_IPG 217
+#define IMX6QDL_CLK_END 218
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */