diff options
| author | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:34:05 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 01:34:05 -0700 |
| commit | eacb128fe92c1c242045202eb354e22803f14f42 (patch) | |
| tree | d2ce7b27f3050d5d3e29dd56c3c12153a87fc784 /include | |
| parent | 0411e20ff8785034b48dfbe508527b71ab72c9c0 (diff) | |
| parent | c480a1b5117c05b82e49e143c037642cc4b53c77 (diff) | |
Merge branch 'buckets/media' into after-buckets
Diffstat (limited to 'include')
30 files changed, 2769 insertions, 0 deletions
diff --git a/include/linux/tegra_avp.h b/include/linux/tegra_avp.h new file mode 100644 index 000000000000..9dc92f821368 --- /dev/null +++ b/include/linux/tegra_avp.h @@ -0,0 +1,44 @@ +/* + * Copyright (C) 2010 Google, Inc. + * Author: Dima Zavin <dima@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_AVP_H +#define __LINUX_TEGRA_AVP_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#define TEGRA_AVP_LIB_MAX_NAME 32 +#define TEGRA_AVP_LIB_MAX_ARGS 220 /* DO NOT CHANGE THIS! */ + +struct tegra_avp_lib { + char name[TEGRA_AVP_LIB_MAX_NAME]; + void __user *args; + size_t args_len; + int greedy; + unsigned long handle; +}; + +struct tegra_avp_platform_data { + unsigned long emc_clk_rate; +}; +#define TEGRA_AVP_IOCTL_MAGIC 'r' + +#define TEGRA_AVP_IOCTL_LOAD_LIB _IOWR(TEGRA_AVP_IOCTL_MAGIC, 0x40, struct tegra_avp_lib) +#define TEGRA_AVP_IOCTL_UNLOAD_LIB _IOW(TEGRA_AVP_IOCTL_MAGIC, 0x41, unsigned long) + +#define TEGRA_AVP_IOCTL_MIN_NR _IOC_NR(TEGRA_AVP_IOCTL_LOAD_LIB) +#define TEGRA_AVP_IOCTL_MAX_NR _IOC_NR(TEGRA_AVP_IOCTL_UNLOAD_LIB) + +#endif diff --git a/include/linux/tegra_mediaserver.h b/include/linux/tegra_mediaserver.h new file mode 100644 index 000000000000..f28473baf63e --- /dev/null +++ b/include/linux/tegra_mediaserver.h @@ -0,0 +1,112 @@ +/* include/linux/tegra_mediaserver.h + * + * Media Server driver for NVIDIA Tegra SoCs + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + + +#ifndef _TEGRA_MEDIASERVER_H +#define _TEGRA_MEDIASERVER_H + +#include <linux/ioctl.h> + +#define TEGRA_MEDIASERVER_MAGIC 'm' +#define TEGRA_MEDIASERVER_IOCTL_ALLOC \ + _IOWR(TEGRA_MEDIASERVER_MAGIC, 0x40, \ + union tegra_mediaserver_alloc_info) + +enum tegra_mediaserver_resource_type { + TEGRA_MEDIASERVER_RESOURCE_BLOCK = 0, + TEGRA_MEDIASERVER_RESOURCE_IRAM, +}; + +enum tegra_mediaserver_block_type { + TEGRA_MEDIASERVER_BLOCK_AUDDEC = 0, + TEGRA_MEDIASERVER_BLOCK_VIDDEC, +}; + +enum tegra_mediaserver_iram_type { + TEGRA_MEDIASERVER_IRAM_SCRATCH = 0, + TEGRA_MEDIASERVER_IRAM_SHARED, +}; + + +struct tegra_mediaserver_block_info { + int nvmm_block_handle; + int avp_block_handle; + int avp_block_library_handle; + int service_handle; + int service_library_handle; +}; + +struct tegra_mediaserver_iram_info { + unsigned long rm_handle; + int physical_address; +}; + +union tegra_mediaserver_alloc_info { + struct { + int tegra_mediaserver_resource_type; + + union { + struct tegra_mediaserver_block_info block; + + struct { + int tegra_mediaserver_iram_type; + int alignment; + size_t size; + } iram; + } u; + } in; + + struct { + union { + struct { + int count; + } block; + + struct tegra_mediaserver_iram_info iram; + } u; + } out; +}; + + +#define TEGRA_MEDIASERVER_IOCTL_FREE \ + _IOR(TEGRA_MEDIASERVER_MAGIC, 0x41, union tegra_mediaserver_free_info) + +union tegra_mediaserver_free_info { + struct { + int tegra_mediaserver_resource_type; + + union { + int nvmm_block_handle; + int iram_rm_handle; + } u; + } in; +}; + + +#define TEGRA_MEDIASERVER_IOCTL_UPDATE_BLOCK_INFO \ + _IOR(TEGRA_MEDIASERVER_MAGIC, 0x45, \ + union tegra_mediaserver_update_block_info) + +union tegra_mediaserver_update_block_info { + struct tegra_mediaserver_block_info in; +}; +#endif + diff --git a/include/linux/tegra_nvavp.h b/include/linux/tegra_nvavp.h new file mode 100644 index 000000000000..250eee379de9 --- /dev/null +++ b/include/linux/tegra_nvavp.h @@ -0,0 +1,100 @@ +/* + * include/linux/tegra_nvavp.h + * + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __LINUX_TEGRA_NVAVP_H +#define __LINUX_TEGRA_NVAVP_H + +#include <linux/ioctl.h> +#include <linux/types.h> + +#define NVAVP_MAX_RELOCATION_COUNT 64 + +/* avp submit flags */ +#define NVAVP_FLAG_NONE 0x00000000 +#define NVAVP_UCODE_EXT 0x00000001 /*use external ucode provided */ + +enum { + NVAVP_MODULE_ID_AVP = 2, + NVAVP_MODULE_ID_VCP = 3, + NVAVP_MODULE_ID_BSEA = 27, + NVAVP_MODULE_ID_VDE = 28, + NVAVP_MODULE_ID_MPE = 29, + NVAVP_MODULE_ID_EMC = 75, +}; + +struct nvavp_cmdbuf { + __u32 mem; + __u32 offset; + __u32 words; +}; + +struct nvavp_reloc { + __u32 cmdbuf_mem; + __u32 cmdbuf_offset; + __u32 target; + __u32 target_offset; +}; + +struct nvavp_syncpt { + __u32 id; + __u32 value; +}; + +struct nvavp_pushbuffer_submit_hdr { + struct nvavp_cmdbuf cmdbuf; + struct nvavp_reloc *relocs; + __u32 num_relocs; + struct nvavp_syncpt *syncpt; + __u32 flags; +}; + +struct nvavp_set_nvmap_fd_args { + __u32 fd; +}; + +struct nvavp_clock_args { + __u32 id; + __u32 rate; +}; + +enum nvavp_clock_stay_on_state { + NVAVP_CLOCK_STAY_ON_DISABLED = 0, + NVAVP_CLOCK_STAY_ON_ENABLED +}; + +struct nvavp_clock_stay_on_state_args { + enum nvavp_clock_stay_on_state state; +}; + +#define NVAVP_IOCTL_MAGIC 'n' + +#define NVAVP_IOCTL_SET_NVMAP_FD _IOW(NVAVP_IOCTL_MAGIC, 0x60, \ + struct nvavp_set_nvmap_fd_args) +#define NVAVP_IOCTL_GET_SYNCPOINT_ID _IOR(NVAVP_IOCTL_MAGIC, 0x61, \ + __u32) +#define NVAVP_IOCTL_PUSH_BUFFER_SUBMIT _IOWR(NVAVP_IOCTL_MAGIC, 0x63, \ + struct nvavp_pushbuffer_submit_hdr) +#define NVAVP_IOCTL_SET_CLOCK _IOWR(NVAVP_IOCTL_MAGIC, 0x64, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_GET_CLOCK _IOR(NVAVP_IOCTL_MAGIC, 0x65, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_WAKE_AVP _IOR(NVAVP_IOCTL_MAGIC, 0x66, \ + __u32) +#define NVAVP_IOCTL_FORCE_CLOCK_STAY_ON _IOW(NVAVP_IOCTL_MAGIC, 0x67, \ + struct nvavp_clock_stay_on_state_args) +#define NVAVP_IOCTL_ENABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x68, \ + struct nvavp_clock_args) +#define NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x69, \ + struct nvavp_clock_args) + +#define NVAVP_IOCTL_MIN_NR _IOC_NR(NVAVP_IOCTL_SET_NVMAP_FD) +#define NVAVP_IOCTL_MAX_NR _IOC_NR(NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS) + +#endif /* __LINUX_TEGRA_NVAVP_H */ diff --git a/include/linux/tegra_rpc.h b/include/linux/tegra_rpc.h new file mode 100644 index 000000000000..16e6367cf569 --- /dev/null +++ b/include/linux/tegra_rpc.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Dima Zavin <dima@android.com> + * + * Based on original code from NVIDIA, and a partial rewrite by: + * Gary King <gking@nvidia.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_RPC_H +#define __LINUX_TEGRA_RPC_H + +#define TEGRA_RPC_MAX_MSG_LEN 256 + +/* Note: the actual size of the name in the protocol message is 16 bytes, + * but that is because the name there is not NUL terminated, only NUL + * padded. */ +#define TEGRA_RPC_MAX_NAME_LEN 17 + +struct tegra_rpc_port_desc { + char name[TEGRA_RPC_MAX_NAME_LEN]; + int notify_fd; /* fd representing a trpc_sema to signal when a + * message has been received */ +}; + +#define TEGRA_RPC_IOCTL_MAGIC 'r' + +#define TEGRA_RPC_IOCTL_PORT_CREATE _IOW(TEGRA_RPC_IOCTL_MAGIC, 0x20, struct tegra_rpc_port_desc) +#define TEGRA_RPC_IOCTL_PORT_GET_NAME _IOR(TEGRA_RPC_IOCTL_MAGIC, 0x21, char *) +#define TEGRA_RPC_IOCTL_PORT_CONNECT _IOR(TEGRA_RPC_IOCTL_MAGIC, 0x22, long) +#define TEGRA_RPC_IOCTL_PORT_LISTEN _IOR(TEGRA_RPC_IOCTL_MAGIC, 0x23, long) + +#define TEGRA_RPC_IOCTL_MIN_NR _IOC_NR(TEGRA_RPC_IOCTL_PORT_CREATE) +#define TEGRA_RPC_IOCTL_MAX_NR _IOC_NR(TEGRA_RPC_IOCTL_PORT_LISTEN) + +#endif diff --git a/include/linux/tegra_sema.h b/include/linux/tegra_sema.h new file mode 100644 index 000000000000..7b423b6cb5c4 --- /dev/null +++ b/include/linux/tegra_sema.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2010 Google, Inc. + * + * Author: + * Dima Zavin <dima@android.com> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __LINUX_TEGRA_SEMA_H +#define __LINUX_TEGRA_SEMA_H + +/* this shares the magic with the tegra RPC and AVP drivers. + * See include/linux/tegra_avp.h and include/linux/tegra_rpc.h */ +#define TEGRA_SEMA_IOCTL_MAGIC 'r' + +/* If IOCTL_WAIT is interrupted by a signal and the timeout was not -1, + * then the value pointed to by the argument will be updated with the amount + * of time remaining for the wait. */ +#define TEGRA_SEMA_IOCTL_WAIT _IOW(TEGRA_SEMA_IOCTL_MAGIC, 0x30, long *) +#define TEGRA_SEMA_IOCTL_SIGNAL _IO(TEGRA_SEMA_IOCTL_MAGIC, 0x31) + +#define TEGRA_SEMA_IOCTL_MIN_NR _IOC_NR(TEGRA_SEMA_IOCTL_WAIT) +#define TEGRA_SEMA_IOCTL_MAX_NR _IOC_NR(TEGRA_SEMA_IOCTL_SIGNAL) + +#endif diff --git a/include/media/ad5816.h b/include/media/ad5816.h new file mode 100644 index 000000000000..30baa5f46c4b --- /dev/null +++ b/include/media/ad5816.h @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2011-2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __AD5816_H__ +#define __AD5816_H__ + +#include <media/nvc_focus.h> +#include <media/nvc.h> + +struct ad5816_power_rail { + struct regulator *vdd; + struct regulator *vdd_i2c; +}; + +struct ad5816_platform_data { + int cfg; + int num; + int sync; + const char *dev_name; + struct nvc_focus_nvc (*nvc); + struct nvc_focus_cap (*cap); + struct ad5816_pdata_info (*info); + int gpio_count; + struct nvc_gpio_pdata *gpio; + int (*power_on)(struct ad5816_power_rail *pw); + int (*power_off)(struct ad5816_power_rail *pw); +}; + +struct ad5816_pdata_info { + float focal_length; + float fnumber; + __u32 settle_time; + __s16 pos_low; + __s16 pos_high; + __s16 limit_low; + __s16 limit_high; + int move_timeoutms; + __u32 focus_hyper_ratio; + __u32 focus_hyper_div; +}; + +// Register Definitions +#define IC_INFO 0x00 +#define IC_VERSION 0x01 +#define CONTROL 0x02 +#define VCM_CODE_MSB 0x03 +#define VCM_CODE_LSB 0x04 +#define STATUS 0x05 +#define MODE 0x06 +#define VCM_FREQ 0x07 +#define VCM_THRESHOLD 0x08 +#define SCL_LOW_DETECTION 0xC0 + + +#endif +/* __AD5816_H__ */ diff --git a/include/media/ad5820.h b/include/media/ad5820.h new file mode 100644 index 000000000000..c3e710113402 --- /dev/null +++ b/include/media/ad5820.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010-2011 NVIDIA Corporation. + * + * Contributors: + * Sachin Nikam <snikam@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __AD5820_H__ +#define __AD5820_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define AD5820_IOCTL_GET_CONFIG _IOR('o', 1, struct ad5820_config) +#define AD5820_IOCTL_SET_POSITION _IOW('o', 2, u32) + +struct ad5820_config { + __u32 settle_time; + __u32 actuator_range; + __u32 pos_low; + __u32 pos_high; + float focal_length; + float fnumber; + float max_aperture; +}; + +#endif /* __AD5820_H__ */ + diff --git a/include/media/ar0832_main.h b/include/media/ar0832_main.h new file mode 100644 index 000000000000..3cc1afcb941a --- /dev/null +++ b/include/media/ar0832_main.h @@ -0,0 +1,99 @@ +/* +* ar0832_main.h +* +* Copyright (c) 2011, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __AR0832_MAIN_H__ +#define __AR0832_MAIN_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ +#include <media/nvc_focus.h> + +#define AR0832_IOCTL_SET_MODE _IOW('o', 0x01, struct ar0832_mode) +#define AR0832_IOCTL_SET_FRAME_LENGTH _IOW('o', 0x02, __u32) +#define AR0832_IOCTL_SET_COARSE_TIME _IOW('o', 0x03, __u32) +#define AR0832_IOCTL_SET_GAIN _IOW('o', 0x04, __u16) +#define AR0832_IOCTL_GET_STATUS _IOR('o', 0x05, __u8) +#define AR0832_IOCTL_GET_OTP _IOR('o', 0x06, struct ar0832_otp_data) +#define AR0832_IOCTL_TEST_PATTERN _IOW('o', 0x07, enum ar0832_test_pattern) +#define AR0832_IOCTL_SET_POWER_ON _IOW('o', 0x08, struct ar0832_mode) +#define AR0832_IOCTL_SET_SENSOR_REGION _IOW('o', 0x09, struct ar0832_stereo_region) + +#define AR0832_FOCUSER_IOCTL_GET_CONFIG _IOR('o', 0x10, struct nv_focuser_config) +#define AR0832_FOCUSER_IOCTL_SET_POSITION _IOW('o', 0x11, __u32) + +#define AR0832_IOCTL_GET_SENSOR_ID _IOR('o', 0x12, __u16) +#define AR0832_FOCUSER_IOCTL_SET_CONFIG _IOW('o', 0x13, struct nv_focuser_config) + +#define AR0832_SENSOR_ID_8141 0x1006 +#define AR0832_SENSOR_ID_8140 0x3006 + +enum ar0832_test_pattern { + TEST_PATTERN_NONE, + TEST_PATTERN_COLORBARS, + TEST_PATTERN_CHECKERBOARD +}; + +struct ar0832_otp_data { + /* Only the first 5 bytes are actually used. */ + __u8 sensor_serial_num[6]; + __u8 part_num[8]; + __u8 lens_id[1]; + __u8 manufacture_id[2]; + __u8 factory_id[2]; + __u8 manufacture_date[9]; + __u8 manufacture_line[2]; + + __u32 module_serial_num; + __u8 focuser_liftoff[2]; + __u8 focuser_macro[2]; + __u8 reserved1[12]; + __u8 shutter_cal[16]; + __u8 reserved2[183]; + + /* Big-endian. CRC16 over 0x00-0x41 (inclusive) */ + __u16 crc; + __u8 reserved3[3]; + __u8 auto_load[2]; +} __attribute__ ((packed)); + +struct ar0832_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; + int stereo; +}; + +struct ar0832_point{ + int x; + int y; +}; + +struct ar0832_reg { + __u16 addr; + __u16 val; +}; + +struct ar0832_stereo_region { + int camera_index; + struct ar0832_point image_start; + struct ar0832_point image_end; +}; + + +#ifdef __KERNEL__ +struct ar0832_platform_data { + int (*power_on)(struct device *, int is_stereo); + int (*power_off)(struct device *, int is_stereo); + char *id; +}; +#endif /* __KERNEL__ */ + +#endif diff --git a/include/media/as364x.h b/include/media/as364x.h new file mode 100644 index 000000000000..c1872b5fe27b --- /dev/null +++ b/include/media/as364x.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __AS364X_H__ +#define __AS364X_H__ + +#include <media/nvc_torch.h> + +enum { + AS3643, + AS3647, + AS3648, + AS364X_NUM, +}; + +struct as364x_config { + bool use_tx_mask; /* enable TXMASK */ + u16 I_limit_mA; /* AS3647/AS3648: 2000, 2500, 3000, 3500 mA + * AS3643: 1000, 1500, 2000, 2500 mA for the coil*/ + u16 txmasked_current_mA; /* 57,113,...847, roughly 56.47 mA steps */ + u16 vin_low_v_run_mV; /* 0xffff=off, 3000, 3070, 3140, 3220, 3300, + 3338, 3470 mV battery limit for dynamic flash + reduction */ + u16 vin_low_v_mV; /* 0xffff=off, 3000, 3070, 3140, 3220, 3300, 3338, + 3470mV battery limit for flash denial */ + u8 strobe_type; /* 1=edge, 2=level */ + u8 inct_pwm; /* pwm duty cycle for indicator or low current mode */ + bool freq_switch_on; + /* balance the current sinks for unmatched LED forward valtages */ + bool load_balance_on; + bool led_off_when_vin_low; /* if 0 txmask current is used */ + bool boost_mode; /* all LED current are increased by 11% */ + /* LED configuration, two identical leds must be connected. */ + u16 max_total_current_mA; /* Both leds' maximum peak current in mA */ + u16 max_peak_current_mA; /* This led's maximum peak current in mA */ + u16 max_peak_duration_ms; /* the maximum duration max_peak_current_mA + can be applied */ + u16 max_sustained_current_mA; /* This leds maximum sustained current + in mA */ + u16 min_current_mA; /* This leds minimum current in mA, desired + values smaller than this will be realised + using PWM. */ +}; + +struct as364x_power_rail { + struct regulator *v_in; + struct regulator *v_i2c; +}; + +struct as364x_platform_data { + struct as364x_config config; + u32 type; /* flash device type, refer to as364x_type */ + u32 led_mask; /* which led(s) enabled, 1/2/3 - left/right/both */ + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state pinstate; /* see notes in driver */ + unsigned gpio_strobe; /* GPIO connected to the ACT signal */ + bool strobe_low_act; /* strobe state active low */ + + int (*power_on_callback)(struct as364x_power_rail *pw); + int (*power_off_callback)(struct as364x_power_rail *pw); +}; + +#endif +/* __AS364X_H__ */ diff --git a/include/media/imx091.h b/include/media/imx091.h new file mode 100644 index 000000000000..7f56765cd528 --- /dev/null +++ b/include/media/imx091.h @@ -0,0 +1,59 @@ +/* +* imx091.h +* +* Copyright (c) 2012, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __IMX091_H__ +#define __IMX091_H__ + +#include <media/nvc.h> +#include <media/nvc_image.h> + +/* See notes in the nvc.h file on the GPIO usage */ +enum imx091_gpio { + IMX091_GPIO_RESET = 0, + IMX091_GPIO_PWDN, + IMX091_GPIO_GP1, +}; + +/* The enumeration must be in the order the regulators are to be enabled */ +/* See Power Requirements note in the driver */ +enum imx091_vreg { + IMX091_VREG_DVDD = 0, + IMX091_VREG_AVDD, + IMX091_VREG_IOVDD, +}; + +struct imx091_flash_config { + u8 xvs_trigger_enabled; + u8 sdo_trigger_enabled; + u8 adjustable_flash_timing; + u16 pulse_width_uS; +}; + +struct imx091_platform_data { + unsigned cfg; + unsigned num; + unsigned sync; + const char *dev_name; + unsigned gpio_count; /* see nvc.h GPIO notes */ + struct nvc_gpio_pdata *gpio; /* see nvc.h GPIO notes */ + struct imx091_flash_config flash_cap; + struct nvc_imager_cap *cap; + unsigned lens_focal_length; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_max_aperture; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_fnumber; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_h; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_v; /* / _INT2FLOAT_DIVISOR */ + struct edp_client edpc_config; + int (*probe_clock)(unsigned long); + int (*power_on)(struct nvc_regulator *); + int (*power_off)(struct nvc_regulator *); +}; + +#endif /* __IMX091_H__ */ diff --git a/include/media/imx132.h b/include/media/imx132.h new file mode 100644 index 000000000000..01d7c67d94b7 --- /dev/null +++ b/include/media/imx132.h @@ -0,0 +1,70 @@ +/** + * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * NVIDIA Corporation and its licensors retain all intellectual property + * and proprietary rights in and to this software and related documentation + * and any modifications thereto. Any use, reproduction, disclosure or + * distribution of this software and related documentation without an express + * license agreement from NVIDIA Corporation is strictly prohibited. + */ + +#ifndef __IMX132_H__ +#define __IMX132_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define IMX132_IOCTL_SET_MODE _IOW('o', 1, struct imx132_mode) +#define IMX132_IOCTL_GET_STATUS _IOR('o', 2, __u8) +#define IMX132_IOCTL_SET_FRAME_LENGTH _IOW('o', 3, __u32) +#define IMX132_IOCTL_SET_COARSE_TIME _IOW('o', 4, __u32) +#define IMX132_IOCTL_SET_GAIN _IOW('o', 5, __u16) +#define IMX132_IOCTL_GET_SENSORDATA _IOR('o', 6, struct imx132_sensordata) +#define IMX132_IOCTL_SET_GROUP_HOLD _IOW('o', 7, struct imx132_ae) + +/* IMX132 registers */ +#define IMX132_GROUP_PARAM_HOLD (0x0104) +#define IMX132_COARSE_INTEGRATION_TIME_15_8 (0x0202) +#define IMX132_COARSE_INTEGRATION_TIME_7_0 (0x0203) +#define IMX132_ANA_GAIN_GLOBAL (0x0205) +#define IMX132_FRAME_LEN_LINES_15_8 (0x0340) +#define IMX132_FRAME_LEN_LINES_7_0 (0x0341) + +#define NUM_OF_FRAME_LEN_REG 2 +#define NUM_OF_COARSE_TIME_REG 2 +#define NUM_OF_SENSOR_ID_SPECIFIC_REG 8 +struct imx132_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct imx132_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __s32 gain; + __u8 gain_enable; +}; + +struct imx132_sensordata { + __u32 fuse_id_size; + __u8 fuse_id[16]; +}; + +#ifdef __KERNEL__ +struct imx132_power_rail { + struct regulator *dvdd; + struct regulator *avdd; + struct regulator *iovdd; +}; + +struct imx132_platform_data { + int (*power_on)(struct imx132_power_rail *pw); + int (*power_off)(struct imx132_power_rail *pw); +}; +#endif /* __KERNEL__ */ + +#endif /* __IMX132_H__ */ diff --git a/include/media/max77665-flash.h b/include/media/max77665-flash.h new file mode 100644 index 000000000000..fc1edc6917c5 --- /dev/null +++ b/include/media/max77665-flash.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __MAX77665_H__ +#define __MAX77665_H__ + +#include <media/nvc_torch.h> + +struct max77665_f_power_rail { + /* to enable the module power */ + struct regulator *vbus; + /* to enable the host interface power */ + struct regulator *vio; + /* to enable the power on i2c bus */ + struct regulator *i2c; +}; + +struct max77665_f_led_config { + u16 color_setting; + u16 flash_torch_ratio; /* max flash to max torch ratio, in 1/1000 */ + u16 granularity; /* 1, 10, 100, ... to carry float settings */ + u16 flash_levels; /* calibrated flash levels < 32 */ + /* this table contains the calibrated flash level - luminance pair */ + struct nvc_torch_lumi_level_v1 *lumi_levels; +}; + +struct max77665_f_config { + u32 led_mask; /* led(s) enabled, 1/2/3 - left/right/both */ + bool synchronized_led; /* if both leds enabled, consider as one. */ + bool flash_on_torch; /* true=high level on the torch_en pin will + turn on flash */ + u16 flash_mode; /* 1=one_shot_mode, flash is triggerred on the + rising edge of FLASHEN/TORCHEN/I2C_bit, and + terminated based on the flash safety timer + value. + 0, 2=run for MAX timer, flash is triggerred + on the rising edge of FLASHEN/TORCHEN/I2C, + and terminated based on the falling edge of + FLASHEN/TORCHEN/I2C_bit and flash safety + timer value, whichever comes first.*/ + u16 torch_trigger_mode; /* 0, 3=torch is triggered via i2c interface. + 1=high level on the flash_en pin will turn + the torch on. + 2=high level on the torch_en pin will turn + the torch on. */ + u16 torch_mode; /* 1=torch safety timer disabled, torch is + controlled solely by the FLASHEN/TORCHEN/I2C. + 2=one_shot_mode, torch is triggerred on the + rising edge of FLASHEN/TORCHEN/I2C_bit, and + terminated based on the torch safety timer + setting. + 0, 3=run MAX timer, torch is triggerred on + the rising edge of FLASHEN/TORCHEN/I2C_bit, + and terminated based on the falling edge of + FLASHEN/TORCHEN/ I2C_bit and torch safety + timer setting, whichever comes first.*/ + u16 adaptive_mode; /* 1=fix mode, 2=adaptive mode + The BYP starts from BOOST_VOUT_FLASH value. + Then increment by 100mV steps until there is + full programmed current across the LED(s). + Fixed mode otherwise: the BYP stays at + BOOST_VOUT_FLASH value */ + u16 boost_vout_flash_mV; /* BOOST_VOUT_FLASH value */ + /* LED configuration, two identical leds must be connected. */ + u16 max_total_current_mA; /* Both leds' maximum peak current in mA */ + u16 max_peak_current_mA; /* This led's maximum peak current in mA */ + u16 max_torch_current_mA; /* This leds maximum torch current in mA */ + u16 max_peak_duration_ms; /* the maximum duration max_peak_current_mA + can be applied */ + u16 max_flash_threshold_mV; /* low battery detection threshold. + 2400mV ~ 3400mV. */ + u16 max_flash_hysteresis_mV; /* low battery detection hysteresis. + 100mV ~ 300mV */ + u16 max_flash_lbdly_f_uS; /* Low battery delay timer for falling edge + detection. Adjustable from 256uS to + 2048uS in 256uS steps. */ + u16 max_flash_lbdly_r_uS; /* Low battery delay timer for raising edge + detection. Adjustable from 256uS to + 2048uS in 256uS steps. */ + struct max77665_f_led_config led_config[2]; +}; + +struct max77665_f_platform_data { + struct max77665_f_config config; + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state pinstate; /* see notes in driver */ + unsigned gpio_strobe; /* GPIO connected to the ACT signal */ + struct edp_client edpc_config; + + int (*poweron_callback)(struct max77665_f_power_rail *pw); + int (*poweroff_callback)(struct max77665_f_power_rail *pw); +}; + +#endif +/* __MAX77665_H__ */ diff --git a/include/media/nvc.h b/include/media/nvc.h new file mode 100644 index 000000000000..ec5d6aecc44d --- /dev/null +++ b/include/media/nvc.h @@ -0,0 +1,286 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_H__ +#define __NVC_H__ + +#include <linux/ioctl.h> + +#define NVC_INT2FLOAT_DIVISOR_1K 1000 +#define NVC_INT2FLOAT_DIVISOR_1M 1000000 +#define NVC_INT2FLOAT_DIVISOR 1000 + +struct nvc_param { + int param; + __u32 sizeofvalue; + void *p_value; +} __packed; + +enum nvc_params { + NVC_PARAM_EXPOSURE = 0, + NVC_PARAM_GAIN, + NVC_PARAM_FRAMERATE, + NVC_PARAM_MAX_FRAMERATE, + NVC_PARAM_INPUT_CLOCK, + NVC_PARAM_LOCUS, + NVC_PARAM_FLASH_CAPS, + NVC_PARAM_FLASH_LEVEL, + NVC_PARAM_FLASH_PIN_STATE, + NVC_PARAM_TORCH_CAPS, + NVC_PARAM_TORCH_LEVEL, + NVC_PARAM_FOCAL_LEN, + NVC_PARAM_MAX_APERTURE, + NVC_PARAM_FNUMBER, + NVC_PARAM_EXPOSURE_LIMITS, + NVC_PARAM_GAIN_LIMITS, + NVC_PARAM_FRAMERATE_LIMITS, + NVC_PARAM_FRAME_RATES, + NVC_PARAM_CLOCK_LIMITS, + NVC_PARAM_EXP_LATCH_TIME, + NVC_PARAM_REGION_USED, + NVC_PARAM_CALIBRATION_DATA, + NVC_PARAM_CALIBRATION_OVERRIDES, + NVC_PARAM_SELF_TEST, + NVC_PARAM_STS, + NVC_PARAM_TESTMODE, + NVC_PARAM_EXPECTED_VALUES, + NVC_PARAM_RESET, + NVC_PARAM_OPTIMIZE_RES, + NVC_PARAM_DETECT_COLOR_TEMP, + NVC_PARAM_LINES_PER_SEC, + NVC_PARAM_CAPS, + NVC_PARAM_CUSTOM_BLOCK_INFO, + NVC_PARAM_STEREO_CAP, + NVC_PARAM_FOCUS_STEREO, + NVC_PARAM_STEREO, + NVC_PARAM_INHERENT_GAIN, + NVC_PARAM_VIEW_ANGLE_H, + NVC_PARAM_VIEW_ANGLE_V, + NVC_PARAM_ISP_SETTING, + NVC_PARAM_OPERATION_MODE, + NVC_PARAM_SUPPORT_ISP, + NVC_PARAM_AWB_LOCK, + NVC_PARAM_AE_LOCK, + NVC_PARAM_RES_CHANGE_WAIT_TIME, + NVC_PARAM_FACTORY_CALIBRATION_DATA, + NVC_PARAM_DEV_ID, + NVC_PARAM_GROUP_HOLD, + NVC_PARAM_SET_SENSOR_FLASH_MODE, + NVC_PARAM_BEGIN_VENDOR_EXTENSIONS = 0x10000000, + NVC_PARAM_CALIBRATION_STATUS, + NVC_PARAM_TEST_PATTERN, + NVC_PARAM_MODULE_INFO, + NVC_PARAM_FLASH_MAX_POWER, + NVC_PARAM_DIRECTION, + NVC_PARAM_SENSOR_TYPE, + NVC_PARAM_DLI_CHECK, + NVC_PARAM_PARALLEL_DLI_CHECK, + NVC_PARAM_BRACKET_CAPS, + NVC_PARAM_NUM, + NVC_PARAM_I2C, + NVC_PARAM_FORCE32 = 0x7FFFFFFF +}; + +/* sync off */ +#define NVC_SYNC_OFF 0 +/* use only this device (the one receiving the call) */ +#define NVC_SYNC_MASTER 1 +/* use only the synced device (the "other" device) */ +#define NVC_SYNC_SLAVE 2 +/* use both synced devices at the same time */ +#define NVC_SYNC_STEREO 3 + +#define NVC_RESET_HARD 0 +#define NVC_RESET_SOFT 1 + +struct nvc_param_isp { + int attr; + void *p_data; + __u32 data_size; +} __packed; + +struct nvc_isp_focus_param { + __s32 min_pos; + __s32 max_pos; + __s32 hyperfocal; + __s32 macro; + __s32 powersave; +} __packed; + +struct nvc_isp_focus_pos { + __u32 is_auto; + __s32 value; +} __packed; + +struct nvc_isp_focus_region { + __u32 num_region; + __s32 value; +} __packed; + +enum nvc_params_isp { + NVC_PARAM_ISP_FOCUS_CAF = 16389, + NVC_PARAM_ISP_FOCUS_CAF_PAUSE, + NVC_PARAM_ISP_FOCUS_CAF_STS, + NVC_PARAM_ISP_FOCUS_POS = 16407, + NVC_PARAM_ISP_FOCUS_RANGE, + NVC_PARAM_ISP_FOCUS_AF_RGN = 16413, + NVC_PARAM_ISP_FOCUS_AF_RGN_MASK, + NVC_PARAM_ISP_FOCUS_AF_RGN_STS, + NVC_PARAM_ISP_FOCUS_CTRL = 16424, + NVC_PARAM_ISP_FOCUS_TRGR, + NVC_PARAM_ISP_FOCUS_STS, +}; + +#define NVC_PARAM_ISP_FOCUS_STS_BUSY 0 +#define NVC_PARAM_ISP_FOCUS_STS_LOCKD 1 +#define NVC_PARAM_ISP_FOCUS_STS_FAILD 2 +#define NVC_PARAM_ISP_FOCUS_STS_ERR 3 + +#define NVC_PARAM_ISP_FOCUS_CTRL_ON 0 +#define NVC_PARAM_ISP_FOCUS_CTRL_OFF 1 +#define NVC_PARAM_ISP_FOCUS_CTRL_AUTO 2 +#define NVC_PARAM_ISP_FOCUS_CTRL_ALOCK 3 + +#define NVC_PARAM_ISP_FOCUS_CAF_CONVRG 1 +#define NVC_PARAM_ISP_FOCUS_CAF_SEARCH 2 + +#define NVC_PARAM_ISP_FOCUS_POS_INF 0 + + +#define NVC_IOCTL_PWR_WR _IOW('o', 102, int) +#define NVC_IOCTL_PWR_RD _IOW('o', 103, int) +#define NVC_IOCTL_PARAM_WR _IOW('o', 104, struct nvc_param) +#define NVC_IOCTL_PARAM_RD _IOWR('o', 105, struct nvc_param) +#define NVC_IOCTL_PARAM_ISP_RD _IOWR('o', 200, struct nvc_param_isp) +#define NVC_IOCTL_PARAM_ISP_WR _IOWR('o', 201, struct nvc_param_isp) + + +#ifdef __KERNEL__ + +#include <linux/regulator/consumer.h> + +/* The NVC_CFG_ defines are for the .cfg entry in the + * platform data structure. + */ +/* Device not registered if not found */ +#define NVC_CFG_NODEV (1 << 0) +/* Don't return errors */ +#define NVC_CFG_NOERR (1 << 1) +/* Always go to _PWR_STDBY instead of _PWR_OFF */ +#define NVC_CFG_OFF2STDBY (1 << 2) +/* Init device at sys boot */ +#define NVC_CFG_BOOT_INIT (1 << 3) +/* Sync mode uses an I2C MUX to send at same time */ +#define NVC_CFG_SYNC_I2C_MUX (1 << 4) + +/* Expected higher level power calls are: + * 1 = OFF + * 2 = STANDBY + * 3 = ON + * These will be multiplied by 2 before given to the driver's PM code that + * uses the _PWR_ defines. This allows us to insert defines to give more power + * granularity and still remain linear with regards to the power usage and + * full power state transition latency for easy implementation of PM + * algorithms. + * The PM actions: + * _PWR_ERR = Non-valid state. + * _PWR_OFF_FORCE = _PWR_OFF is forced regardless of standby mechanisms. + * _PWR_OFF = Device, regulators, clocks, etc is turned off. The longest + * transition time to _PWR_ON is from this state. + * _PWR_STDBY_OFF = Device is useless but powered. No communication possible. + * Device does not retain programming. Main purpose is for + * faster return to _PWR_ON without regulator delays. + * _PWR_STDBY = Device is in standby. Device retains programming. + * _PWR_COMM = Device is powered enough to communicate with the device. + * _PWR_ON = Device is at full power with active output. + * + * The kernel drivers treat these calls as Guaranteed Level Of Service. + */ + +#define NVC_PWR_ERR 0 +#define NVC_PWR_OFF_FORCE 1 +#define NVC_PWR_OFF 2 +#define NVC_PWR_STDBY_OFF 3 +#define NVC_PWR_STDBY 4 +#define NVC_PWR_COMM 5 +#define NVC_PWR_ON 6 + +struct nvc_regulator_init { + unsigned vreg_num; + const char *vreg_name; +}; + +struct nvc_regulator { + bool vreg_flag; + struct regulator *vreg; + const char *vreg_name; +}; + +/* The GPIO mechanism uses the _gpio_type in the device's header file as a key + * to define all the possible GPIO's the device will need. The key is used to + * combine the GPIO's defined in the platform board file using the + * nvc_gpio_pdata structure with the nvc_gpio structure in the nvc kernel + * driver. + */ +struct nvc_gpio_pdata { + /* use a _gpio_type enum from the device's header file */ + unsigned gpio_type; + /* the GPIO system number */ + unsigned gpio; + /* init_en is typically set to true for all GPIO's used by the driver. + * However, some GPIO's are used by multiple drivers (CSI MUX, reset, + * etc.). In this case, this is set true for only one of the drivers + * that uses the GPIO and false for the others. If the platform board + * file initializes the GPIO, then this is false for all of the drivers + * using the GPIO. + */ + bool init_en; + /* this defines the assert level for the general purpose GPIO's + * (_GPIO_TYPE_GPx, etc.). The _GPIO_TYPE_GPx can be used for a GPIO + * that the driver doesn't know about but is needed in order for the + * device to work (CSI select, regulator, etc.). The driver will + * blindly assert the GPIO when the device is operational and deassert + * when the device is turned off. + */ + bool active_high; +}; + +struct nvc_gpio_init { + /* key to match in nvc_gpio_pdata */ + unsigned gpio_type; + /* same as in gpio.h */ + unsigned long flags; + /* same as in gpio.h */ + const char *label; + /* used instead of nvc_gpio_pdata.active_high if use_flags true */ + bool active_high; + /* false if nvc_gpio_pdata.active_high used else flags is used */ + bool use_flags; +}; + +struct nvc_gpio { + unsigned gpio; /* system GPIO number */ + bool own; /* gets set if driver initializes */ + bool active_high; /* used for GP GPIOs */ + bool valid; /* set if struct data is valid */ + bool flag; /* scratch flag for driver implementation */ +}; + +#endif /* __KERNEL__ */ + +#endif /* __NVC_H__ */ + diff --git a/include/media/nvc_focus.h b/include/media/nvc_focus.h new file mode 100644 index 000000000000..4874cf1b7ee4 --- /dev/null +++ b/include/media/nvc_focus.h @@ -0,0 +1,114 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_FOCUS_H__ +#define __NVC_FOCUS_H__ + +/* NVC_FOCUS_CAP_VER0: invalid */ +/* NVC_FOCUS_CAP_VER1: + * __u32 version + * __u32 actuator_range + * __u32 settle_time + */ +#define NVC_FOCUS_CAP_VER1 1 +/* NVC_FOCUS_CAP_VER2 adds: + * __u32 focus_macro; + * __u32 focus_hyper; + * __u32 focus_infinity; + */ +#define NVC_FOCUS_CAP_VER2 2 +#define NVC_FOCUS_CAP_VER 2 /* latest version */ + +#define AF_POS_INVALID_VALUE INT_MAX + +/* These are the slew rate values coming down from the configuration */ +/* Disabled is the same as fastest. Default is the default */ +/* slew rate configuration in the focuser */ +#define SLEW_RATE_DISABLED 0 +#define SLEW_RATE_DEFAULT 1 +#define SLEW_RATE_SLOWEST 9 + + +enum nvc_focus_sts { + NVC_FOCUS_STS_UNKNOWN = 1, + NVC_FOCUS_STS_NO_DEVICE, + NVC_FOCUS_STS_INITIALIZING, + NVC_FOCUS_STS_INIT_ERR, + NVC_FOCUS_STS_WAIT_FOR_MOVE_END, + NVC_FOCUS_STS_WAIT_FOR_SETTLE, + NVC_FOCUS_STS_LENS_SETTLED, + NVC_FOCUS_STS_FORCE32 = 0x7FFFFFFF +}; + +struct nvc_focus_nvc { + __u32 focal_length; + __u32 fnumber; + __u32 max_aperature; +} __packed; + +struct nvc_focus_cap { + __u32 version; + __s32 actuator_range; + __u32 settle_time; + __s32 focus_macro; + __s32 focus_hyper; + __s32 focus_infinity; + __u32 slew_rate; + __u32 position_translate; +} __packed; + + +#define NV_FOCUSER_SET_MAX 10 +#define NV_FOCUSER_SET_DISTANCE_PAIR 16 + +struct nv_focuser_set_dist_pairs { + __s32 fdn; + __s32 distance; +} __packed; + +struct nv_focuser_set { + __s32 posture; + __s32 macro; + __s32 hyper; + __s32 inf; + __s32 hysteresis; + __u32 settle_time; + __s32 macro_offset; + __s32 inf_offset; + __u32 num_dist_pairs; + struct nv_focuser_set_dist_pairs + dist_pair[NV_FOCUSER_SET_DISTANCE_PAIR]; +} __packed; + +struct nv_focuser_config { + __u32 focal_length; + __u32 fnumber; + __u32 max_aperture; + __u32 range_ends_reversed; + __s32 pos_working_low; + __s32 pos_working_high; + __s32 pos_actual_low; + __s32 pos_actual_high; + __u32 slew_rate; + __u32 circle_of_confusion; + __u32 num_focuser_sets; + struct nv_focuser_set focuser_set[NV_FOCUSER_SET_MAX]; +} __packed; + + +#endif /* __NVC_FOCUS_H__ */ + diff --git a/include/media/nvc_image.h b/include/media/nvc_image.h new file mode 100644 index 000000000000..aa56a4103a55 --- /dev/null +++ b/include/media/nvc_image.h @@ -0,0 +1,256 @@ +/* Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_IMAGE_H__ +#define __NVC_IMAGE_H__ + +#include <linux/ioctl.h> + +#define NVC_IMAGER_API_CAPS_VER 2 +#define NVC_IMAGER_API_STATIC_VER 1 +#define NVC_IMAGER_API_DYNAMIC_VER 1 +#define NVC_IMAGER_API_BAYER_VER 1 + +#define NVC_IMAGER_TEST_NONE 0 +#define NVC_IMAGER_TEST_COLORBARS 1 +#define NVC_IMAGER_TEST_CHECKERBOARD 2 +#define NVC_IMAGER_TEST_WALKING1S 3 + +#define NVC_IMAGER_CROPMODE_NONE 1 +#define NVC_IMAGER_CROPMODE_PARTIAL 2 + +#define NVC_IMAGER_TYPE_HUH 0 +#define NVC_IMAGER_TYPE_RAW 1 +#define NVC_IMAGER_TYPE_SOC 2 + +/** + * Defines camera imager types. + * Mirrors "NvOdmImagerRegion" in "imager/include/nvodm_imager.h". + * These must remain in sync. + */ +#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_8 1 +#define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_10 2 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_A 3 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_B 4 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_C 5 +#define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_AB 6 +#define NVC_IMAGER_SENSOR_INTERFACE_CCIR 7 +#define NVC_IMAGER_SENSOR_INTERFACE_HOST 8 +#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_A 9 +#define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_B 10 +#define NVC_IMAGER_SENSOR_INTERFACE_NUM 11 + +#define NVC_IMAGER_IDENTIFIER_MAX 32 +#define NVC_IMAGER_FORMAT_MAX 4 +#define NVC_IMAGER_CLOCK_PROFILE_MAX 2 +#define NVC_IMAGER_CAPABILITIES_VERSION2 ((0x3434 << 16) | 2) + +#define NVC_IMAGER_INT2FLOAT_DIVISOR 1000 + +#define NVC_FOCUS_INTERNAL (0x665F4E5643414D69ULL) +#define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF)) +#define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF)) + + +struct nvc_imager_static_nvc { + __u32 api_version; + __u32 sensor_type; + __u32 bits_per_pixel; + __u32 sensor_id; + __u32 sensor_id_minor; + __u32 focal_len; + __u32 max_aperture; + __u32 fnumber; + __u32 view_angle_h; + __u32 view_angle_v; + __u32 stereo_cap; + __u32 res_chg_wait_time; + __u8 support_isp; + __u8 align1; + __u8 align2; + __u8 align3; + __u8 fuse_id[16]; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_dynamic_nvc { + __u32 api_version; + __s32 region_start_x; + __s32 region_start_y; + __u32 x_scale; + __u32 y_scale; + __u32 bracket_caps; + __u32 flush_count; + __u32 init_intra_frame_skip; + __u32 ss_intra_frame_skip; + __u32 ss_frame_number; + __u32 coarse_time; + __u32 max_coarse_diff; + __u32 min_exposure_course; + __u32 max_exposure_course; + __u32 diff_integration_time; + __u32 line_length; + __u32 frame_length; + __u32 min_frame_length; + __u32 max_frame_length; + __u32 min_gain; + __u32 max_gain; + __u32 inherent_gain; + __u32 inherent_gain_bin_en; + __u8 support_bin_control; + __u8 support_fast_mode; + __u8 align2; + __u8 align3; + __u32 pll_mult; + __u32 pll_div; + __u32 mode_sw_wait_frames; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; +} __packed; + +struct nvc_imager_bayer { + __u32 api_version; + __s32 res_x; + __s32 res_y; + __u32 frame_length; + __u32 coarse_time; + __u32 gain; + __u8 bin_en; + __u8 align1; + __u8 align2; + __u8 align3; + __u32 place_holder1; + __u32 place_holder2; + __u32 place_holder3; + __u32 place_holder4; +} __packed; + +struct nvc_imager_mode { + __s32 res_x; + __s32 res_y; + __s32 active_start_x; + __s32 active_stary_y; + __u32 peak_frame_rate; + __u32 pixel_aspect_ratio; + __u32 pll_multiplier; + __u32 crop_mode; + __u32 rect_left; + __u32 rect_top; + __u32 rect_right; + __u32 rect_bottom; + __u32 point_x; + __u32 point_y; + __u32 type; +} __packed; + +struct nvc_imager_dnvc { + __s32 res_x; + __s32 res_y; + struct nvc_imager_mode *p_mode; + struct nvc_imager_dynamic_nvc *p_dnvc; +} __packed; + +struct nvc_imager_mode_list { + struct nvc_imager_mode *p_modes; + __u32 *p_num_mode; +} __packed; + +struct nvc_clock_profile { + __u32 external_clock_khz; + __u32 clock_multiplier; +} __packed; + +struct nvc_imager_cap { + char identifier[NVC_IMAGER_IDENTIFIER_MAX]; + __u32 sensor_nvc_interface; + __u32 pixel_types[NVC_IMAGER_FORMAT_MAX]; + __u32 orientation; + __u32 direction; + __u32 initial_clock_rate_khz; + struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX]; + __u32 h_sync_edge; + __u32 v_sync_edge; + __u32 mclk_on_vgp0; + __u8 csi_port; + __u8 data_lanes; + __u8 virtual_channel_id; + __u8 discontinuous_clk_mode; + __u8 cil_threshold_settle; + __u8 align1; + __u8 align2; + __u8 align3; + __s32 min_blank_time_width; + __s32 min_blank_time_height; + __u32 preferred_mode_index; + __u64 focuser_guid; + __u64 torch_guid; + __u32 cap_version; + __u8 flash_control_enabled; + __u8 adjustable_flash_timing; + __u8 align4; + __u8 align5; +} __packed; + +struct nvc_imager_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __u32 gain; + __u8 gain_enable; +} __packed; + +union nvc_imager_flash_control { + __u16 mode; + struct { + __u16 enable:1; /* enable the on-sensor flash control */ + __u16 edge_trig_en:1; /* two types of flash controls: + * 0 - LED_FLASH_EN - supports continued + * flash level only, doesn't + * support start edge/repeat/dly. + * 1 - FLASH_EN - supports control pulse + * control pulse attributes are + * defined below. + */ + __u16 start_edge:1; /* flash control pulse rise position: + * 0 - at the start of the next frame. + * 1 - at the effective pixel end + * position of the next frame. + */ + __u16 repeat:1; /* flash control pulse repeat: + * 0 - only triggers one frame. + * 1 - trigger repeats every frame until + * Flash_EN = 0. + */ + __u16 delay_frm:2; /* flash control pulse can be delayed + * in frame units: (0 - 3) - frame + * numbers the pulse is delayed. + */ + } settings; +}; + +#define NVC_IOCTL_CAPS_RD _IOWR('o', 106, struct nvc_imager_cap) +#define NVC_IOCTL_MODE_WR _IOW('o', 107, struct nvc_imager_bayer) +#define NVC_IOCTL_MODE_RD _IOWR('o', 108, struct nvc_imager_mode_list) +#define NVC_IOCTL_STATIC_RD _IOWR('o', 109, struct nvc_imager_static_nvc) +#define NVC_IOCTL_DYNAMIC_RD _IOWR('o', 110, struct nvc_imager_dnvc) + +#endif /* __NVC_IMAGE_H__ */ diff --git a/include/media/nvc_torch.h b/include/media/nvc_torch.h new file mode 100644 index 000000000000..3acdc0cb6ce6 --- /dev/null +++ b/include/media/nvc_torch.h @@ -0,0 +1,113 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __NVC_TORCH_H__ +#define __NVC_TORCH_H__ + +struct nvc_torch_level_info { + __s32 guidenum; + __u32 sustaintime; + __s32 rechargefactor; +} __packed; + +struct nvc_torch_pin_state { + __u16 mask; + __u16 values; +} __packed; + +struct nvc_torch_flash_capabilities { + __u32 numberoflevels; + struct nvc_torch_level_info levels[]; +} __packed; + +struct nvc_torch_torch_capabilities { + __u32 numberoflevels; + __s32 guidenum[]; +} __packed; + +/* advanced flash/torch capability settings */ +/* use version number to distinguish between different capability structures */ +#define NVC_TORCH_LED_ATTR_FLASH_SYNC 1 +#define NVC_TORCH_LED_ATTR_IND_FTIMER (1 << 1) +#define NVC_TORCH_LED_ATTR_TORCH_SYNC (1 << 16) +#define NVC_TORCH_LED_ATTR_IND_TTIMER (1 << 17) + +struct nvc_torch_capability_query { + __u8 version; + __u8 flash_num; /* number of flashes supported by this device */ + __u8 torch_num; /* number of torches supported by this device */ + __u8 reserved; + __u32 led_attr; +}; + +#define NVC_TORCH_CAPABILITY_LEGACY 0 +#define NVC_TORCH_CAPABILITY_VER_1 1 + +struct nvc_torch_set_level_v1 { + __u16 ledmask; + __u16 timeout; + /* flash/torch levels mapped to ledmask for lsb to msb respectively */ + __u16 levels[2]; +}; + +struct nvc_torch_lumi_level_v1 { + __u16 guidenum; + __u32 luminance; + __u32 reserved; +}; + +struct nvc_torch_timeout_v1 { + __u32 timeout; + __u32 reserved1; +}; + +struct nvc_torch_timer_capabilities_v1 { + __u32 timeout_num; + /* time out durations in uS */ + struct nvc_torch_timeout_v1 timeouts[]; +}; + +struct nvc_torch_flash_capabilities_v1 { + __u8 version; /* fixed number 1 */ + __u8 led_idx; + __u8 reserved1; + __u8 reserved2; + __u32 attribute; + __u16 granularity; /* 1, 10, 100, ... to carry float settings */ + __u16 flash_torch_ratio; + __u32 timeout_num; + __u32 timeout_off; + __u32 numberoflevels; + struct nvc_torch_lumi_level_v1 levels[]; +}; + +struct nvc_torch_torch_capabilities_v1 { + __u8 version; /* fixed number 1 */ + __u8 led_idx; + __u8 reserved1; + __u8 reserved2; + __u32 attribute; + __u16 granularity; /* 1, 10, 100, ... to carry float settings */ + __u16 reserved4; + __u32 timeout_num; + __u32 timeout_off; + __u32 numberoflevels; + struct nvc_torch_lumi_level_v1 levels[]; +}; + +#endif /* __NVC_TORCH_H__ */ + diff --git a/include/media/ov14810.h b/include/media/ov14810.h new file mode 100644 index 000000000000..c9d6e8147ecd --- /dev/null +++ b/include/media/ov14810.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV14810_H__ +#define __OV14810_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV14810_IOCTL_SET_MODE _IOW('o', 1, struct ov14810_mode) +#define OV14810_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV14810_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV14810_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV14810_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV14810_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) +#define OV14810_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) + +struct ov14810_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; +#ifdef __KERNEL__ +struct ov14810_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + void (*synchronize_sensors)(void); +}; +#endif /* __KERNEL__ */ + +#endif /* __OV14810_H__ */ diff --git a/include/media/ov2710.h b/include/media/ov2710.h new file mode 100644 index 000000000000..a3e070b5ade4 --- /dev/null +++ b/include/media/ov2710.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2010 Motorola, Inc. + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV2710_H__ +#define __OV2710_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV2710_IOCTL_SET_MODE _IOW('o', 1, struct ov2710_mode) +#define OV2710_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV2710_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV2710_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV2710_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV2710_IOCTL_SET_GROUP_HOLD _IOW('o', 6, struct ov2710_ae) + +struct ov2710_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov2710_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __s32 gain; + __u8 gain_enable; +}; + +#ifdef __KERNEL__ +struct ov2710_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + +}; +#endif /* __KERNEL__ */ + +#endif /* __OV2710_H__ */ + diff --git a/include/media/ov5640.h b/include/media/ov5640.h new file mode 100644 index 000000000000..da6be4d1d441 --- /dev/null +++ b/include/media/ov5640.h @@ -0,0 +1,73 @@ +/* + * ov5640.h - header for YUV camera sensor OV5640 driver. + * + * Copyright (C) 2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV5640_H__ +#define __OV5640_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV5640_IOCTL_SET_SENSOR_MODE _IOW('o', 1, struct ov5640_mode) +#define OV5640_IOCTL_GET_SENSOR_STATUS _IOR('o', 2, __u8) +#define OV5640_IOCTL_GET_CONFIG _IOR('o', 3, struct ov5640_config) +#define OV5640_IOCTL_SET_FPOSITION _IOW('o', 4, __u32) +#define OV5640_IOCTL_POWER_LEVEL _IOW('o', 5, __u32) +#define OV5640_IOCTL_GET_AF_STATUS _IOR('o', 6, __u8) +#define OV5640_IOCTL_SET_AF_MODE _IOR('o', 7, __u8) +#define OV5640_IOCTL_SET_WB _IOR('o', 9, __u8) + +#define OV5640_POWER_LEVEL_OFF 0 +#define OV5640_POWER_LEVEL_ON 1 +#define OV5640_POWER_LEVEL_SUS 2 + +struct ov5640_mode { + int xres; + int yres; +}; + +struct ov5640_config { + __u32 settle_time; + __u32 pos_low; + __u32 pos_high; + float focal_length; + float fnumber; +}; + +enum { + OV5640_AF_INIFINITY, + OV5640_AF_TRIGGER, +}; + +enum { + OV5640_WB_AUTO, + OV5640_WB_INCANDESCENT, + OV5640_WB_DAYLIGHT, + OV5640_WB_FLUORESCENT, + OV5640_WB_CLOUDY, +}; + +#ifdef __KERNEL__ +struct ov5640_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + +}; +#endif /* __KERNEL__ */ + +#endif /* __OV5640_H__ */ diff --git a/include/media/ov5650.h b/include/media/ov5650.h new file mode 100644 index 000000000000..f1f2f67acd56 --- /dev/null +++ b/include/media/ov5650.h @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2010 Motorola, Inc. + * Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __OV5650_H__ +#define __OV5650_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define OV5650_IOCTL_SET_MODE _IOW('o', 1, struct ov5650_mode) +#define OV5650_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV5650_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV5650_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV5650_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV5650_IOCTL_SET_BINNING _IOW('o', 6, __u8) +#define OV5650_IOCTL_TEST_PATTERN _IOW('o', 7, enum ov5650_test_pattern) +#define OV5650_IOCTL_SET_GROUP_HOLD _IOW('o', 8, struct ov5650_ae) +#define OV5650_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) +#define OV5650_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) +#define OV5650_IOCTL_GET_SENSORDATA _IOR('o', 12, struct ov5650_sensordata) + +/* OV5650 registers */ +#define OV5650_SRM_GRUP_ACCESS (0x3212) +#define OV5650_ARRAY_CONTROL_01 (0x3621) +#define OV5650_ANALOG_CONTROL_D (0x370D) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_CONTROL_HS_HIGH (0x3800) +#define OV5650_TIMING_CONTROL_HS_LOW (0x3801) +#define OV5650_TIMING_CONTROL_VS_HIGH (0x3802) +#define OV5650_TIMING_CONTROL_VS_LOW (0x3803) +#define OV5650_TIMING_HW_HIGH (0x3804) +#define OV5650_TIMING_HW_LOW (0x3805) +#define OV5650_TIMING_VH_HIGH (0x3806) +#define OV5650_TIMING_VH_LOW (0x3807) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_HREFST_MAN_HIGH (0x3824) +#define OV5650_TIMING_HREFST_MAN_LOW (0x3825) +#define OV5650_H_BINNING_BIT (1 << 7) +#define OV5650_H_SUBSAMPLING_BIT (1 << 6) +#define OV5650_V_BINNING_BIT (1 << 6) +#define OV5650_V_SUBSAMPLING_BIT (1 << 0) +#define OV5650_GROUP_HOLD_BIT (1 << 7) +#define OV5650_GROUP_LAUNCH_BIT (1 << 5) +#define OV5650_GROUP_HOLD_END_BIT (1 << 4) +#define OV5650_GROUP_ID(id) (id) + +enum ov5650_test_pattern { + TEST_PATTERN_NONE, + TEST_PATTERN_COLORBARS, + TEST_PATTERN_CHECKERBOARD +}; + +struct ov5650_sensordata { + __u32 fuse_id_size; + __u8 fuse_id[16]; +}; + +struct ov5650_mode { + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov5650_ae { + __u32 frame_length; + __u8 frame_length_enable; + __u32 coarse_time; + __u8 coarse_time_enable; + __s32 gain; + __u8 gain_enable; +}; + +#ifdef __KERNEL__ +struct ov5650_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + void (*synchronize_sensors)(void); +}; +#endif /* __KERNEL__ */ + +#endif /* __OV5650_H__ */ + diff --git a/include/media/ov9726.h b/include/media/ov9726.h new file mode 100644 index 000000000000..e942000380b4 --- /dev/null +++ b/include/media/ov9726.h @@ -0,0 +1,72 @@ +/* +* ov9726.h +* +* Copyright (c) 2011, NVIDIA, All Rights Reserved. +* +* This file is licensed under the terms of the GNU General Public License +* version 2. This program is licensed "as is" without any warranty of any +* kind, whether express or implied. +*/ + +#ifndef __OV9726_H__ +#define __OV9726_H__ + +#include <linux/ioctl.h> + +#define OV9726_I2C_ADDR 0x20 + +#define OV9726_IOCTL_SET_MODE _IOW('o', 1, struct ov9726_mode) +#define OV9726_IOCTL_SET_FRAME_LENGTH _IOW('o', 2, __u32) +#define OV9726_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) +#define OV9726_IOCTL_SET_GAIN _IOW('o', 4, __u16) +#define OV9726_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV9726_IOCTL_SET_GROUP_HOLD _IOW('o', 6, struct ov9726_ae) + +struct ov9726_mode { + int mode_id; + int xres; + int yres; + __u32 frame_length; + __u32 coarse_time; + __u16 gain; +}; + +struct ov9726_ae { + __u32 frame_length; + __u32 coarse_time; + __u16 gain; + __u8 frame_length_enable; + __u8 coarse_time_enable; + __u8 gain_enable; +}; + +struct ov9726_reg { + __u16 addr; + __u16 val; +}; + +#ifdef __KERNEL__ +#define OV9726_REG_FRAME_LENGTH_HI 0x340 +#define OV9726_REG_FRAME_LENGTH_LO 0x341 +#define OV9726_REG_COARSE_TIME_HI 0x202 +#define OV9726_REG_COARSE_TIME_LO 0x203 +#define OV9726_REG_GAIN_HI 0x204 +#define OV9726_REG_GAIN_LO 0x205 + +#define OV9726_MAX_RETRIES 3 + +#define OV9726_TABLE_WAIT_MS 0 +#define OV9726_TABLE_END 1 + +struct ov9726_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + unsigned gpio_rst; + bool rst_low_active; + unsigned gpio_pwdn; + bool pwdn_low_active; +}; +#endif /* __KERNEL__ */ + +#endif /* __OV9726_H__ */ + diff --git a/include/media/ov9772.h b/include/media/ov9772.h new file mode 100644 index 000000000000..82075b7e384e --- /dev/null +++ b/include/media/ov9772.h @@ -0,0 +1,53 @@ +/* + * nvc_ov9772.h - ov9772 sensor driver + * + * * Copyright (c) 2012 NVIDIA Corporation. All rights reserved. + * + * Contributors: + * Phil Breczinski <pbreczinski@nvidia.com> + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#ifndef __OV9772_H__ +#define __OV9772_H__ + +#include <media/nvc.h> +#include <media/nvc_image.h> + +/* See notes in the nvc.h file on the GPIO usage */ +enum ov9772_gpio_type { + OV9772_GPIO_TYPE_SHTDN = 0, + OV9772_GPIO_TYPE_PWRDN, + OV9772_GPIO_TYPE_I2CMUX, + OV9772_GPIO_TYPE_GP1, + OV9772_GPIO_TYPE_GP2, + OV9772_GPIO_TYPE_GP3, +}; + +struct ov9772_power_rail { + struct regulator *dvdd; + struct regulator *avdd; + struct regulator *dovdd; +}; + +struct ov9772_platform_data { + unsigned cfg; + unsigned num; + unsigned sync; + const char *dev_name; + unsigned gpio_count; + struct nvc_gpio_pdata *gpio; /* see nvc.h GPIO notes */ + struct nvc_imager_cap *cap; + unsigned lens_focal_length; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_max_aperture; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_fnumber; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_h; /* / _INT2FLOAT_DIVISOR */ + unsigned lens_view_angle_v; /* / _INT2FLOAT_DIVISOR */ + int (*probe_clock)(unsigned long); + int (*power_on)(struct ov9772_power_rail *); + int (*power_off)(struct ov9772_power_rail *); +}; +#endif /* __OV9772_H__ */ diff --git a/include/media/sh532u.h b/include/media/sh532u.h new file mode 100644 index 000000000000..e9653e68b21f --- /dev/null +++ b/include/media/sh532u.h @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2011-2012 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __SH532U_H__ +#define __SH532U_H__ + +#include <media/nvc.h> +#include <media/nvc_focus.h> + +/* See notes in the nvc.h file on the GPIO usage */ +enum sh532u_gpio { + SH532U_GPIO_RESET = 0, + SH532U_GPIO_I2CMUX, + SH532U_GPIO_GP1, + SH532U_GPIO_GP2, + SH532U_GPIO_GP3, +}; + +/* The enumeration must be in the order the regulators are to be enabled */ +/* See Power Requirements note in the driver */ +enum sh532u_vreg { + SH532U_VREG_DVDD = 0, + SH532U_VREG_AVDD, +}; + +struct sh532u_pdata_info { + __s16 pos_low; + __s16 pos_high; + __s16 limit_low; + __s16 limit_high; + int move_timeoutms; + __u32 focus_hyper_ratio; + __u32 focus_hyper_div; +}; + +struct sh532u_platform_data { + unsigned cfg; + unsigned num; + unsigned sync; + const char *dev_name; + unsigned gpio_count; /* see nvc.h GPIO notes */ + struct nvc_gpio_pdata *gpio; /* see nvc.h GPIO notes */ + struct nvc_focus_nvc (*nvc); + struct nvc_focus_cap (*cap); + struct sh532u_pdata_info (*info); + __u8 i2c_addr_rom; +}; + +/* Register Definition : Sany Driver IC */ +/* EEPROM addresses */ +#define addrHallOffset 0x10 +#define addrHallBias 0x11 +#define addrInf1 0x12 +#define addrMac1 0x13 +#define addrLoopGainH 0x14 +#define addrLoopGainL 0x15 +#define addrInf2 0x16 +#define addrMac2 0x17 + +#define addrInf1_H 0x20 /* bottom mechanical limit of HVCA */ +#define addrInf1_L 0x21 +#define addrMac1_H 0x22 /* top mechanical limit of HVCA */ +#define addrMac1_L 0x23 +#define addrInf2_H 0x24 /* lens position when object is ?120cm */ +#define addrInf2_L 0x25 +#define addrMac2_H 0x26 /* lens position when object is ?10cm */ +#define addrMac2_L 0x27 +#define addrDacDeltaUp_H 0x28 /* difference between face up and down */ +#define addrDacDeltaUp_L 0x29 +#define addrAFoffset_H 0x2A /* best focus position subtract value */ +#define addrAFoffset_L 0x2B + +/* Convergence Judgement */ +#define INI_MSSET_211 0x00 +#define CHTGOKN_TIME 0x80 +#define CHTGOKN_WAIT 1 +#define CHTGOKN_TIMEOUT 50 +#define CHTGSTOKN_TOMEOUT 15 + +/* StepMove */ +#define STMV_SIZE 0x0180 + +#define STMCHTG_ON 0x08 +#define STMSV_ON 0x04 +#define STMLFF_ON 0x02 +#define STMVEN_ON 0x01 +#define STMCHTG_OFF 0x00 +#define STMSV_OFF 0x00 +#define STMLFF_OFF 0x00 +#define STMVEN_OFF 0x00 + +#define STMCHTG_SET STMCHTG_ON +#define STMSV_SET STMSV_ON +#define STMLFF_SET STMLFF_OFF + +#define CHTGST_ON 0x01 +#define DEFAULT_DADAT 0x8040 + +/* Delay RAM 00h ~ 3Fh */ +#define ADHXI_211H 0x00 +#define ADHXI_211L 0x01 +#define PIDZO_211H 0x02 +#define PIDZO_211L 0x03 +#define RZ_211H 0x04 +#define RZ_211L 0x05 +#define DZ1_211H 0x06 +#define DZ1_211L 0x07 +#define DZ2_211H 0x08 +#define DZ2_211L 0x09 +#define UZ1_211H 0x0A +#define UZ1_211L 0x0B +#define UZ2_211H 0x0C +#define UZ2_211L 0x0D +#define IZ1_211H 0x0E +#define IZ1_211L 0x0F +#define IZ2_211H 0x10 +#define IZ2_211L 0x11 +#define MS1Z01_211H 0x12 +#define MS1Z01_211L 0x13 +#define MS1Z11_211H 0x14 +#define MS1Z11_211L 0x15 +#define MS1Z12_211H 0x16 +#define MS1Z12_211L 0x17 +#define MS1Z22_211H 0x18 +#define MS1Z22_211L 0x19 +#define MS2Z01_211H 0x1A +#define MS2Z01_211L 0x1B +#define MS2Z11_211H 0x1C +#define MS2Z11_211L 0x1D +#define MS2Z12_211H 0x1E +#define MS2Z12_211L 0x1F +#define MS2Z22_211H 0x20 +#define MS2Z22_211L 0x21 +#define MS2Z23_211H 0x22 +#define MS2Z23_211L 0x23 +#define OZ1_211H 0x24 +#define OZ1_211L 0x25 +#define OZ2_211H 0x26 +#define OZ2_211L 0x27 +#define DAHLXO_211H 0x28 +#define DAHLXO_211L 0x29 +#define OZ3_211H 0x2A +#define OZ3_211L 0x2B +#define OZ4_211H 0x2C +#define OZ4_211L 0x2D +#define OZ5_211H 0x2E +#define OZ5_211L 0x2F +#define oe_211H 0x30 +#define oe_211L 0x31 +#define MSR1CMAX_211H 0x32 +#define MSR1CMAX_211L 0x33 +#define MSR1CMIN_211H 0x34 +#define MSR1CMIN_211L 0x35 +#define MSR2CMAX_211H 0x36 +#define MSR2CMAX_211L 0x37 +#define MSR2CMIN_211H 0x38 +#define MSR2CMIN_211L 0x39 +#define OFFSET_211H 0x3A +#define OFFSET_211L 0x3B +#define ADOFFSET_211H 0x3C +#define ADOFFSET_211L 0x3D +#define EZ_211H 0x3E +#define EZ_211L 0x3F + +/* Coefficient RAM 40h ~ 7Fh */ +#define ag_211H 0x40 +#define ag_211L 0x41 +#define da_211H 0x42 +#define da_211L 0x43 +#define db_211H 0x44 +#define db_211L 0x45 +#define dc_211H 0x46 +#define dc_211L 0x47 +#define dg_211H 0x48 +#define dg_211L 0x49 +#define pg_211H 0x4A +#define pg_211L 0x4B +#define gain1_211H 0x4C +#define gain1_211L 0x4D +#define gain2_211H 0x4E +#define gain2_211L 0x4F +#define ua_211H 0x50 +#define ua_211L 0x51 +#define uc_211H 0x52 +#define uc_211L 0x53 +#define ia_211H 0x54 +#define ia_211L 0x55 +#define ib_211H 0x56 +#define ib_211L 0x57 +#define i_c_211H 0x58 +#define i_c_211L 0x59 +#define ms11a_211H 0x5A +#define ms11a_211L 0x5B +#define ms11c_211H 0x5C +#define ms11c_211L 0x5D +#define ms12a_211H 0x5E +#define ms12a_211L 0x5F +#define ms12c_211H 0x60 +#define ms12c_211L 0x61 +#define ms21a_211H 0x62 +#define ms21a_211L 0x63 +#define ms21b_211H 0x64 +#define ms21b_211L 0x65 +#define ms21c_211H 0x66 +#define ms21c_211L 0x67 +#define ms22a_211H 0x68 +#define ms22a_211L 0x69 +#define ms22c_211H 0x6A +#define ms22c_211L 0x6B +#define ms22d_211H 0x6C +#define ms22d_211L 0x6D +#define ms22e_211H 0x6E +#define ms22e_211L 0x6F +#define ms23p_211H 0x70 +#define ms23p_211L 0x71 +#define oa_211H 0x72 +#define oa_211L 0x73 +#define oc_211H 0x74 +#define oc_211L 0x75 +#define PX12_211H 0x76 +#define PX12_211L 0x77 +#define PX3_211H 0x78 +#define PX3_211L 0x79 +#define MS2X_211H 0x7A +#define MS2X_211L 0x7B +#define CHTGX_211H 0x7C +#define CHTGX_211L 0x7D +#define CHTGN_211H 0x7E +#define CHTGN_211L 0x7F + +/* Register 80h ~ 9F */ +#define CLKSEL_211 0x80 +#define ADSET_211 0x81 +#define PWMSEL_211 0x82 +#define SWTCH_211 0x83 +#define STBY_211 0x84 +#define CLR_211 0x85 +#define DSSEL_211 0x86 +#define ENBL_211 0x87 +#define ANA1_211 0x88 +#define STMVEN_211 0x8A +#define STPT_211 0x8B +#define SWFC_211 0x8C +#define SWEN_211 0x8D +#define MSNUM_211 0x8E +#define MSSET_211 0x8F +#define DLYMON_211 0x90 +#define MONA_211 0x91 +#define PWMLIMIT_211 0x92 +#define PINSEL_211 0x93 +#define PWMSEL2_211 0x94 +#define SFTRST_211 0x95 +#define TEST_211 0x96 +#define PWMZONE2_211 0x97 +#define PWMZONE1_211 0x98 +#define PWMZONE0_211 0x99 +#define ZONE3_211 0x9A +#define ZONE2_211 0x9B +#define ZONE1_211 0x9C +#define ZONE0_211 0x9D +#define GCTIM_211 0x9E +#define GCTIM_211NU 0x9F +#define STMINT_211 0xA0 +#define STMVENDH_211 0xA1 +#define STMVENDL_211 0xA2 +#define MSNUMR_211 0xA3 +#define ANA2_211 0xA4 + +/* Device ID of HVCA Drive IC */ +#define HVCA_DEVICE_ID 0xE4 + +/* Device ID of E2P ROM */ +#define EEP_DEVICE_ID 0xA0 +#define EEP_PAGE0 0x00 +#define EEP_PAGE1 0x02 +#define EEP_PAGE2 0x04 +#define EEP_PAGE3 0x06 +/* E2P ROM has 1023 bytes. So there are 4 pages memory */ +/* E2PROM Device ID = 1 0 1 0 0 P0 P1 0 */ +/* +P0 P1 +0 0 : Page 0 +0 1 : Page 1 +1 0 : Page 2 +1 1 : Page 3 +*/ +/* Page 0: address 0x000~0x0FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE0 */ +/* Page 1: address 0x100~0x1FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE1 */ +/* Page 2: address 0x200~0x2FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE2 */ +/* Page 3: address 0x300~0x3FF, E2PROM Device ID = E2P_DEVICE_ID|E2P_PAGE3 */ +/* +*/ + +/* E2P data type define of HVCA Initial Value Section */ +#define DIRECT_MODE 0x00 +#define INDIRECT_EEPROM 0x10 +#define INDIRECT_HVCA 0x20 +#define MASK_AND 0x70 +#define MASK_OR 0x80 + +#define DATA_1BYTE 0x01 +#define DATA_2BYTE 0x02 + +#define START_ADDR 0x0030 +#define END_ADDR 0x01BF + +/*Macro define*/ +#if !defined(abs) +#define abs(a) (((a) > 0) ? (a) : -(a)) +#endif + +#endif +/* __SH532U_H__ */ + diff --git a/include/media/soc380.h b/include/media/soc380.h new file mode 100644 index 000000000000..e732cc0fd29e --- /dev/null +++ b/include/media/soc380.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2011, NVIDIA CORPORATION, All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: + * + * Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * Neither the name of NVIDIA CORPORATION nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SOC380_H__ +#define __SOC380_H__ + +#include <linux/ioctl.h> /* For IOCTL macros */ + +#define SOC380_IOCTL_SET_MODE _IOW('o', 1, struct soc380_mode) +#define SOC380_IOCTL_GET_STATUS _IOR('o', 2, struct soc380_status) + +struct soc380_mode { + int xres; + int yres; +}; + +struct soc380_status { + int data; + int status; +}; + +#ifdef __KERNEL__ +struct soc380_platform_data { + int (*power_on)(struct device *); + int (*power_off)(struct device *); + +}; +#endif /* __KERNEL__ */ + +#endif /* __SOC380_H__ */ + diff --git a/include/media/ssl3250a.h b/include/media/ssl3250a.h new file mode 100644 index 000000000000..c4e802fa2efc --- /dev/null +++ b/include/media/ssl3250a.h @@ -0,0 +1,38 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __SSL3250A_H__ +#define __SSL3250A_H__ + +#include <media/nvc_torch.h> + +#define SSL3250A_MAX_TORCH_LEVEL 11 +#define SSL3250A_MAX_FLASH_LEVEL 20 + +struct ssl3250a_platform_data { + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state (*pinstate); /* see notes in driver */ + unsigned max_amp_torch; /* maximum torch value allowed */ + unsigned max_amp_flash; /* maximum flash value allowed */ + unsigned gpio_act; /* GPIO connected to the ACT signal */ +}; + +#endif /* __SSL3250A_H__ */ + diff --git a/include/media/tegra_camera.h b/include/media/tegra_camera.h new file mode 100644 index 000000000000..9dea1485781d --- /dev/null +++ b/include/media/tegra_camera.h @@ -0,0 +1,58 @@ +/* + * include/linux/tegra_camera.h + * + * Copyright (C) 2010 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ +#ifndef TEGRA_CAMERA_H +#define TEGRA_CAMERA_H + +/* this is to enable VI pattern generator (Null Sensor) */ +#define TEGRA_CAMERA_ENABLE_PD2VI_CLK 0x1 + +enum { + TEGRA_CAMERA_MODULE_ISP = 0, + TEGRA_CAMERA_MODULE_VI, + TEGRA_CAMERA_MODULE_CSI, + TEGRA_CAMERA_MODULE_EMC, + TEGRA_CAMERA_MODULE_MAX +}; + +enum { + TEGRA_CAMERA_VI_CLK, + TEGRA_CAMERA_VI_SENSOR_CLK, + TEGRA_CAMERA_EMC_CLK +}; + +struct tegra_camera_clk_info { + uint id; + uint clk_id; + unsigned long rate; + uint flag; /* to inform if any special bits need to enabled/disabled */ +}; + +enum StereoCameraMode { + Main = 0x0, /* Sets the default camera to Main */ + StereoCameraMode_Left = 0x01, /* the left camera is on. */ + StereoCameraMode_Right = 0x02, /* the right camera is on. */ + StereoCameraMode_Stereo = 0x03, /* both cameras are on. */ + StereoCameraMode_Force32 = 0x7FFFFFFF +}; + + +#define TEGRA_CAMERA_IOCTL_ENABLE _IOWR('i', 1, uint) +#define TEGRA_CAMERA_IOCTL_DISABLE _IOWR('i', 2, uint) +#define TEGRA_CAMERA_IOCTL_CLK_SET_RATE \ + _IOWR('i', 3, struct tegra_camera_clk_info) +#define TEGRA_CAMERA_IOCTL_RESET _IOWR('i', 4, uint) + +#endif diff --git a/include/media/tegra_dtv.h b/include/media/tegra_dtv.h new file mode 100644 index 000000000000..798e3e3bf9c0 --- /dev/null +++ b/include/media/tegra_dtv.h @@ -0,0 +1,134 @@ +/* + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEGRA_DTV_H__ +#define __TEGRA_DTV_H__ + +#include <linux/ioctl.h> + +#define TEGRA_DTV_MAGIC 'v' + +#define TEGRA_DTV_IOCTL_START _IO(TEGRA_DTV_MAGIC, 0) +#define TEGRA_DTV_IOCTL_STOP _IO(TEGRA_DTV_MAGIC, 1) + +struct tegra_dtv_hw_config { + int clk_edge; /*< clock edge to be used to sample DTV input signals */ + int byte_swz_enabled; /*< byte order during deserialization */ + int bit_swz_enabled; /*< bit order during deserialization */ + + int protocol_sel; /*< VD pin configuration. */ + int clk_mode; /*< input clock characteristics */ + int fec_size; /*< FEC size */ + int body_size; /*< BODY size */ + int body_valid_sel; /*< VALID signal gate */ + int start_sel; /*< START of the package */ + int err_pol; /*< ERROR pin polarity */ + int psync_pol; /*< PSYNC pin polarity */ + int valid_pol; /*< VALID pin polarity */ +}; + +#define TEGRA_DTV_IOCTL_SET_HW_CONFIG _IOW(TEGRA_DTV_MAGIC, 2, \ + const struct tegra_dtv_hw_config *) +#define TEGRA_DTV_IOCTL_GET_HW_CONFIG _IOR(TEGRA_DTV_MAGIC, 3, \ + struct tegra_dtv_hw_config *) + +/** + * clock edge settings for clk_edge + * + * RISE_EDGE: sample input signal at rising edge + * FALL_EDGE: sample input signal at falling edge + */ +enum { + TEGRA_DTV_CLK_RISE_EDGE = 0, + TEGRA_DTV_CLK_FALL_EDGE, +}; + +/** + * swizzle settings for byte_swz and bit_swz + * + * ENABLE: enable swizzle during deserialization + * DISABLE: disable swizzle during deserialization + * + * If swizzling is enabled then deserialized data will be re-ordered to + * fit the required format for tegra. + * + * For example, if raw BGR data is inputed into DTV interface, the data + * could be swizzled into RGB. + * + * For TS/MPEG-2 stream, please disable this feature. + */ +enum { + TEGRA_DTV_SWZ_DISABLE = 0, + TEGRA_DTV_SWZ_ENABLE, +}; + +/* for selecting the pin configuration for VD(valid). + * NONE : ERROR is tied to 0, PSYNC is tied to 0 + * ERROR: ERROR is tied to VD, PSYNC is tied to 0 + * PSYNC: ERROR is tied to 0, PSYNC is tied to VD + */ +enum { + TEGRA_DTV_PROTOCOL_NONE = 0, + TEGRA_DTV_PROTOCOL_ERROR, + TEGRA_DTV_PROTOCOL_PSYNC, +}; + +enum { + TEGRA_DTV_CLK_DISCONTINUOUS = 0, + TEGRA_DTV_CLK_CONTINUOUS, +}; + +enum { + TEGRA_DTV_BODY_VALID_IGNORE = 0, + TEGRA_DTV_BODY_VALID_GATE, +}; + +enum { + TEGRA_DTV_START_RESERVED = 0, /* never use this */ + TEGRA_DTV_START_PSYNC, + TEGRA_DTV_START_VALID, + TEGRA_DTV_START_BOTH, +}; + +enum { + TEGRA_DTV_ERROR_POLARITY_HIGH = 0, + TEGRA_DTV_ERROR_POLARITY_LOW, +}; + +enum { + TEGRA_DTV_PSYNC_POLARITY_HIGH = 0, + TEGRA_DTV_PSYNC_POLARITY_LOW, +}; + +enum { + TEGRA_DTV_VALID_POLARITY_HIGH = 0, + TEGRA_DTV_VALID_POLARITY_LOW, +}; + +#ifdef __KERNEL__ +enum { + TEGRA_DTV_CLK_POSEDGE, + TEGRA_DTV_CLK_NEGEDGE, +}; + +struct tegra_dtv_platform_data { + unsigned int dma_buf_size; + int clk_edge; + bool byte_swz_enabled; + bool bit_swz_enabled; +}; +#endif /* __KERNEL__ */ + +#endif /* __TEGRA_DTV_H__ */ diff --git a/include/media/tegra_v4l2_camera.h b/include/media/tegra_v4l2_camera.h new file mode 100644 index 000000000000..f6390b6e5609 --- /dev/null +++ b/include/media/tegra_v4l2_camera.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA_CAMERA_H_ +#define _TEGRA_CAMERA_H_ + +#include <linux/regulator/consumer.h> +#include <linux/i2c.h> +#include <linux/nvhost.h> + +enum tegra_camera_port { + TEGRA_CAMERA_PORT_CSI_A = 1, + TEGRA_CAMERA_PORT_CSI_B, + TEGRA_CAMERA_PORT_VIP, +}; + +struct tegra_camera_platform_data { + int (*enable_camera)(struct nvhost_device *ndev); + void (*disable_camera)(struct nvhost_device *ndev); + bool flip_h; + bool flip_v; + enum tegra_camera_port port; + int lanes; /* For CSI port only */ + bool continuous_clk; /* For CSI port only */ +}; + +#endif /* _TEGRA_CAMERA_H_ */ diff --git a/include/media/tps61050.h b/include/media/tps61050.h new file mode 100644 index 000000000000..1c289eb3616e --- /dev/null +++ b/include/media/tps61050.h @@ -0,0 +1,36 @@ +/* Copyright (C) 2011 NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#ifndef __TPS61050_H__ +#define __TPS61050_H__ + +#include <media/nvc_torch.h> + +#define TPS61050_MAX_TORCH_LEVEL 7 +#define TPS61050_MAX_FLASH_LEVEL 8 + +struct tps61050_platform_data { + unsigned cfg; /* use the NVC_CFG_ defines */ + unsigned num; /* see implementation notes in driver */ + unsigned sync; /* see implementation notes in driver */ + const char *dev_name; /* see implementation notes in driver */ + struct nvc_torch_pin_state (*pinstate); /* see notes in driver */ + unsigned max_amp_torch; /* see implementation notes in driver */ + unsigned max_amp_flash; /* see implementation notes in driver */ +}; + +#endif /* __TPS61050_H__ */ diff --git a/include/media/videobuf2-dma-nvmap.h b/include/media/videobuf2-dma-nvmap.h new file mode 100644 index 000000000000..39ae3d3a1d5d --- /dev/null +++ b/include/media/videobuf2-dma-nvmap.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _MEDIA_VIDEOBUF2_DMA_NVMAP_H +#define _MEDIA_VIDEOBUF2_DMA_NVMAP_H + +#include <media/videobuf2-core.h> +#include <linux/dma-mapping.h> + +static inline dma_addr_t +vb2_dma_nvmap_plane_paddr(struct vb2_buffer *vb, unsigned int plane_no) +{ + dma_addr_t *paddr = vb2_plane_cookie(vb, plane_no); + + return *paddr; +} + +void *vb2_dma_nvmap_init_ctx(struct device *dev); +void vb2_dma_nvmap_cleanup_ctx(void *alloc_ctx); + +extern const struct vb2_mem_ops vb2_dma_nvmap_memops; + +#endif |