diff options
| author | Changyeon Jo <cjo@nvidia.com> | 2011-07-28 09:45:50 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-08-17 15:57:13 -0700 |
| commit | f664c6867c23f1d082b9559a451038f06e437792 (patch) | |
| tree | 91cd3706c18b8b2fdf23b08900e1025ce0c9cfb9 /include | |
| parent | 080f91d508cfd009fe57ebe2c90255bc35b020d2 (diff) | |
media: video: ov5650: add 2x2 binning mode control
Add IOCTL (OV5650_IOCTL_SET_BINNING) that user code
can access to registers which have 2x2 binning control
bits.
Bug 835589
Change-Id: I07f8d3536fcdb92e8bae0af294d1a0f8523cefbc
Reviewed-on: http://git-master/r/43727
Tested-by: Changyeon Jo <cjo@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/media/ov5650.h | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/include/media/ov5650.h b/include/media/ov5650.h index d45a952eecf2..00efcec61a5f 100644 --- a/include/media/ov5650.h +++ b/include/media/ov5650.h @@ -27,10 +27,36 @@ #define OV5650_IOCTL_SET_COARSE_TIME _IOW('o', 3, __u32) #define OV5650_IOCTL_SET_GAIN _IOW('o', 4, __u16) #define OV5650_IOCTL_GET_STATUS _IOR('o', 5, __u8) +#define OV5650_IOCTL_SET_BINNING _IOW('o', 6, __u8) #define OV5650_IOCTL_TEST_PATTERN _IOW('o', 7, enum ov5650_test_pattern) #define OV5650_IOCTL_SET_CAMERA_MODE _IOW('o', 10, __u32) #define OV5650_IOCTL_SYNC_SENSORS _IOW('o', 11, __u32) +/* OV5650 registers */ +#define OV5650_SRM_GRUP_ACCESS (0x3212) +#define OV5650_ARRAY_CONTROL_01 (0x3621) +#define OV5650_ANALOG_CONTROL_D (0x370D) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_CONTROL_HS_HIGH (0x3800) +#define OV5650_TIMING_CONTROL_HS_LOW (0x3801) +#define OV5650_TIMING_CONTROL_VS_HIGH (0x3802) +#define OV5650_TIMING_CONTROL_VS_LOW (0x3803) +#define OV5650_TIMING_HW_HIGH (0x3804) +#define OV5650_TIMING_HW_LOW (0x3805) +#define OV5650_TIMING_VH_HIGH (0x3806) +#define OV5650_TIMING_VH_LOW (0x3807) +#define OV5650_TIMING_TC_REG_18 (0x3818) +#define OV5650_TIMING_HREFST_MAN_HIGH (0x3824) +#define OV5650_TIMING_HREFST_MAN_LOW (0x3825) +#define OV5650_H_BINNING_BIT (1 << 7) +#define OV5650_H_SUBSAMPLING_BIT (1 << 6) +#define OV5650_V_BINNING_BIT (1 << 6) +#define OV5650_V_SUBSAMPLING_BIT (1 << 0) +#define OV5650_GROUP_HOLD_BIT (1 << 7) +#define OV5650_GROUP_LAUNCH_BIT (1 << 5) +#define OV5650_GROUP_HOLD_END_BIT (1 << 4) +#define OV5650_GROUP_ID(id) (id) + enum ov5650_test_pattern { TEST_PATTERN_NONE, TEST_PATTERN_COLORBARS, |