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authorRobert Morell <rmorell@nvidia.com>2011-07-15 18:47:06 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-08-29 17:49:50 -0700
commitd4f30a049a1d97b350c415c3f40d5fa57724c8d4 (patch)
treec44eb2954929f2f0e1587d0f6db92d78c6bbacb0 /include
parent9ce011627ad7255153cf78d2c7e5b09a21d16101 (diff)
video: tegra: dc: Separate allocations for U and V
Currently, dc_ext only takes a single nvmap memory ID per overlay, even in the YUV case (the U and V planes are expected to be differentiated using an offset from the beginning of the nvmap allocation). This is problematic for some software flows, such as certain video interlacing algorithms that will vary the luma plane while keeping the chrome plane constant. This change allows dc_ext clients to specify a different nvmap allocation for each of the Y, U, and V planes. If a YUV surface is used and no U or V plane allocation is specified, the old behavior is preserved: the U and V offsets are assumed to be within the same allocation as Y. Note: this changes the behavior of the offset parameter: the old code added offset to offset_u and offset_v when using it. The new code treats all three offsets as relative to the beginning of the allocation. It also fixes a bug in the code where offset was applied twice to the Y plane. I believe this is safe because the presence of this bug means that no existing clients are using offset != 0 (or if they are, they're already broken). Signed-off-by: Robert Morell <rmorell@nvidia.com> Bug 850882 Change-Id: I230e03db25baaae73a3bdc0d45a2aec162b87fa4 Reviewed-on: http://git-master/r/41471 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/video/tegra_dc_ext.h5
1 files changed, 4 insertions, 1 deletions
diff --git a/include/video/tegra_dc_ext.h b/include/video/tegra_dc_ext.h
index 118184849d1b..824afeaf147b 100644
--- a/include/video/tegra_dc_ext.h
+++ b/include/video/tegra_dc_ext.h
@@ -82,8 +82,11 @@ struct tegra_dc_ext_flip_windowattr {
struct timespec timestamp;
__u32 pre_syncpt_id;
__u32 pre_syncpt_val;
+ /* These are optional; if zero, U and V are taken from buff_id */
+ __u32 buff_id_u;
+ __u32 buff_id_v;
/* Leave some wiggle room for future expansion */
- __u32 pad[8];
+ __u32 pad[6];
};
#define TEGRA_DC_EXT_FLIP_N_WINDOWS 3