MLK-13568: ARM: clk-imx7ulp: Add clock tree for m4 core

SAI in M4 domain, and the clock used by SAI is in M4 domain

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

1 files changed, 57 insertions, 1 deletions

diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 1dd7218fcfa5..0a955df4ad8d 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -100,6 +100,62 @@
 #define IMX7ULP_CLK_MIPI_PLL		80
 #define IMX7ULP_CLK_SIRC		81
 
-#define IMX7ULP_CLK_END			82
+#define IMX7ULP_CLK_SCG1_CLKOUT		82
+
+#define IMX7ULP_CLK_END			83
+
+/*cm4 clocks*/
+#define IMX7ULP_CM4_CLK_DUMMY		0
+#define IMX7ULP_CM4_CLK_CKIL		1
+#define IMX7ULP_CM4_CLK_OSC		2
+#define IMX7ULP_CM4_CLK_FIRC		3
+#define IMX7ULP_CM4_CLK_SIRC		4
+
+/* SCG0 */
+#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL	5
+#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV	6
+#define IMX7ULP_CM4_CLK_SPLL		7
+#define IMX7ULP_CM4_CLK_SPLL_VCO	8
+#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1	9
+#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2	10
+#define IMX7ULP_CM4_CLK_SPLL_PFD0	11
+#define IMX7ULP_CM4_CLK_SPLL_PFD1	12
+#define IMX7ULP_CM4_CLK_SPLL_PFD2	13
+#define IMX7ULP_CM4_CLK_SPLL_PFD3	14
+#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL	15
+#define IMX7ULP_CM4_CLK_SPLL_PFD	16
+#define IMX7ULP_CM4_CLK_SPLL_SEL	17
+#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL	18
+#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV	19
+#define IMX7ULP_CM4_CLK_APLL		20
+#define IMX7ULP_CM4_CLK_APLL_VCO	21
+#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1	22
+#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2	23
+#define IMX7ULP_CM4_CLK_APLL_PFD0	24
+#define IMX7ULP_CM4_CLK_APLL_PFD1	25
+#define IMX7ULP_CM4_CLK_APLL_PFD2	26
+#define IMX7ULP_CM4_CLK_APLL_PFD3	27
+#define IMX7ULP_CM4_CLK_APLL_PFD_SEL	28
+#define IMX7ULP_CM4_CLK_APLL_PFD	29
+#define IMX7ULP_CM4_CLK_APLL_SEL	30
+#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV	31
+#define IMX7ULP_CM4_CLK_SYS_SEL		32
+#define IMX7ULP_CM4_CLK_CORE_DIV	33
+#define IMX7ULP_CM4_CLK_BUS_DIV		34
+#define IMX7ULP_CM4_CLK_PLAT_DIV	35
+#define IMX7ULP_CM4_CLK_SLOW_DIV	36
+
+#define IMX7ULP_CM4_CLK_SAI0_SEL	37
+#define IMX7ULP_CM4_CLK_SAI0_DIV	38
+#define IMX7ULP_CM4_CLK_SAI0_ROOT	39
+#define IMX7ULP_CM4_CLK_SAI0_IPG	40
+#define IMX7ULP_CM4_CLK_SAI1_SEL	41
+#define IMX7ULP_CM4_CLK_SAI1_DIV	42
+#define IMX7ULP_CM4_CLK_SAI1_ROOT	43
+#define IMX7ULP_CM4_CLK_SAI1_IPG	44
+
+#define IMX7ULP_CLK_SCG0_CLKOUT		45
+
+#define IMX7ULP_CM4_CLK_END		46
 
 #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */