diff options
| author | Laxman Dewangan <ldewangan@nvidia.com> | 2010-10-19 14:05:15 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2010-11-22 14:53:41 -0800 |
| commit | ff4d0279c458b724d273efd88ee87ff7caf48991 (patch) | |
| tree | 5f3bdaf3425bf75d3d83554b26bb5ca0f47232ac /include | |
| parent | 6678b8e8e8a087955cf60f3dc84abd9b246c956f (diff) | |
[arm/tegra] serial: Support for break on console driver.
There is sysrq feature which works from console with
sending break and then character.
The console driver uses the 8250 driver.
In tegra uart controller, after receiving break, it
needs to clear the rx fifo by reading fifo till empty
to receive the another break/character.
Fixing this issue in 8250 driver.
bug 697978
Change-Id: I4eb71a67bafc186ec9934fce164e28ad86fa0ace
Reviewed-on: http://git-master/r/8736
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/serial_core.h | 3 | ||||
| -rw-r--r-- | include/linux/serial_reg.h | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h index 743f48ac71dc..18d4b99ed61f 100644 --- a/include/linux/serial_core.h +++ b/include/linux/serial_core.h @@ -44,7 +44,8 @@ #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */ #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */ #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */ -#define PORT_MAX_8250 18 /* max port ID */ +#define PORT_TEGRA 19 /* NVIDIA Tegra internal UART */ +#define PORT_MAX_8250 19 /* max port ID */ /* * ARM specific type numbers. These are not currently guaranteed diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 850db2e80510..360e0d7d7113 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -57,6 +57,7 @@ * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 * TI16C752: 8 16 56 60 8 16 32 56 + * TEGRA: 1 4 8 14 16 8 4 1 */ #define UART_FCR_R_TRIG_00 0x00 #define UART_FCR_R_TRIG_01 0x40 @@ -111,6 +112,7 @@ #define UART_MCR_DTR 0x01 /* DTR complement */ #define UART_LSR 5 /* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /* Fifo error */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ |