Merge branch 'clock/next' into next

* clock/next: (122 commits)
  LF-279 clk: imx: scu: ignore cpu resources when do owned check
  clk: s32v234: Enable FlexCAN clock
  clk: s32v234: Add definitions for CAN clocks
  clk: imx: Add missing mipi1_dsi_phy_clk
  LF-202-3 clk: imx: scu: ignore clks not owned
  ...

9 files changed, 155 insertions, 293 deletions

diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h
index e20c43cc36f6..15118e76e353 100644
--- a/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/include/dt-bindings/clock/imx6qdl-clock.h
@@ -273,6 +273,11 @@
 #define IMX6QDL_CLK_MMDC_P0_IPG			263
 #define IMX6QDL_CLK_DCIC1			264
 #define IMX6QDL_CLK_DCIC2			265
-#define IMX6QDL_CLK_END				266
+#define IMX6QDL_CLK_AXI_ALT_SEL			266
+#define IMX6QDL_CLK_LDB_DI0_DIV_7		267
+#define IMX6QDL_CLK_LDB_DI1_DIV_7		268
+#define IMX6QDL_CLK_LDB_DI0_DIV_SEL		269
+#define IMX6QDL_CLK_LDB_DI1_DIV_SEL		270
+#define IMX6QDL_CLK_END				271
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index e6a670e1a3f8..8ee3b08a7c37 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -451,5 +451,8 @@
 #define IMX7D_SNVS_CLK			442
 #define IMX7D_CAAM_CLK			443
 #define IMX7D_KPP_ROOT_CLK		444
-#define IMX7D_CLK_END			445
+#define IMX7D_PXP_IPG_CLK		445
+#define IMX7D_PXP_AXI_CLK		446
+#define IMX7D_CLK_END			447
+
 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/dt-bindings/clock/imx7ulp-clock.h b/include/dt-bindings/clock/imx7ulp-clock.h
index 6f66f9005c81..f8d34fb4378f 100644
--- a/include/dt-bindings/clock/imx7ulp-clock.h
+++ b/include/dt-bindings/clock/imx7ulp-clock.h
@@ -49,15 +49,14 @@
 #define IMX7ULP_CLK_NIC1_DIV		36
 #define IMX7ULP_CLK_NIC1_BUS_DIV	37
 #define IMX7ULP_CLK_NIC1_EXT_DIV	38
-#define IMX7ULP_CLK_MIPI_PLL		39
-#define IMX7ULP_CLK_SIRC		40
-#define IMX7ULP_CLK_SOSC_BUS_CLK	41
-#define IMX7ULP_CLK_FIRC_BUS_CLK	42
-#define IMX7ULP_CLK_SPLL_BUS_CLK	43
-#define IMX7ULP_CLK_HSRUN_SYS_SEL	44
-#define IMX7ULP_CLK_HSRUN_CORE_DIV	45
+#define IMX7ULP_CLK_SIRC		39
+#define IMX7ULP_CLK_SOSC_BUS_CLK	40
+#define IMX7ULP_CLK_FIRC_BUS_CLK	41
+#define IMX7ULP_CLK_SPLL_BUS_CLK	42
+#define IMX7ULP_CLK_HSRUN_SYS_SEL	43
+#define IMX7ULP_CLK_HSRUN_CORE_DIV	44
 
-#define IMX7ULP_CLK_SCG1_END		46
+#define IMX7ULP_CLK_SCG1_END		45
 
 /* PCC2 */
 #define IMX7ULP_CLK_DMA1		0
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 673a8c662340..d7d2a8f3d49e 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -7,287 +7,59 @@
 #ifndef __DT_BINDINGS_CLOCK_IMX_H
 #define __DT_BINDINGS_CLOCK_IMX_H
 
-/* SCU Clocks */
-
-#define IMX_CLK_DUMMY				0
-
-/* CPU */
-#define IMX_A35_CLK					1
-
-/* LSIO SS */
-#define IMX_LSIO_MEM_CLK				2
-#define IMX_LSIO_BUS_CLK				3
-#define IMX_LSIO_PWM0_CLK				10
-#define IMX_LSIO_PWM1_CLK				11
-#define IMX_LSIO_PWM2_CLK				12
-#define IMX_LSIO_PWM3_CLK				13
-#define IMX_LSIO_PWM4_CLK				14
-#define IMX_LSIO_PWM5_CLK				15
-#define IMX_LSIO_PWM6_CLK				16
-#define IMX_LSIO_PWM7_CLK				17
-#define IMX_LSIO_GPT0_CLK				18
-#define IMX_LSIO_GPT1_CLK				19
-#define IMX_LSIO_GPT2_CLK				20
-#define IMX_LSIO_GPT3_CLK				21
-#define IMX_LSIO_GPT4_CLK				22
-#define IMX_LSIO_FSPI0_CLK				23
-#define IMX_LSIO_FSPI1_CLK				24
-
-/* Connectivity SS */
-#define IMX_CONN_AXI_CLK_ROOT				30
-#define IMX_CONN_AHB_CLK_ROOT				31
-#define IMX_CONN_IPG_CLK_ROOT				32
-#define IMX_CONN_SDHC0_CLK				40
-#define IMX_CONN_SDHC1_CLK				41
-#define IMX_CONN_SDHC2_CLK				42
-#define IMX_CONN_ENET0_ROOT_CLK				43
-#define IMX_CONN_ENET0_BYPASS_CLK			44
-#define IMX_CONN_ENET0_RGMII_CLK			45
-#define IMX_CONN_ENET1_ROOT_CLK				46
-#define IMX_CONN_ENET1_BYPASS_CLK			47
-#define IMX_CONN_ENET1_RGMII_CLK			48
-#define IMX_CONN_GPMI_BCH_IO_CLK			49
-#define IMX_CONN_GPMI_BCH_CLK				50
-#define IMX_CONN_USB2_ACLK				51
-#define IMX_CONN_USB2_BUS_CLK				52
-#define IMX_CONN_USB2_LPM_CLK				53
-
-/* HSIO SS */
-#define IMX_HSIO_AXI_CLK				60
-#define IMX_HSIO_PER_CLK				61
-
-/* Display controller SS */
-#define IMX_DC_AXI_EXT_CLK				70
-#define IMX_DC_AXI_INT_CLK				71
-#define IMX_DC_CFG_CLK					72
-#define IMX_DC0_PLL0_CLK				80
-#define IMX_DC0_PLL1_CLK				81
-#define IMX_DC0_DISP0_CLK				82
-#define IMX_DC0_DISP1_CLK				83
-
-/* MIPI-LVDS SS */
-#define IMX_MIPI_IPG_CLK				90
-#define IMX_MIPI0_PIXEL_CLK				100
-#define IMX_MIPI0_BYPASS_CLK				101
-#define IMX_MIPI0_LVDS_PIXEL_CLK			102
-#define IMX_MIPI0_LVDS_BYPASS_CLK			103
-#define IMX_MIPI0_LVDS_PHY_CLK				104
-#define IMX_MIPI0_I2C0_CLK				105
-#define IMX_MIPI0_I2C1_CLK				106
-#define IMX_MIPI0_PWM0_CLK				107
-#define IMX_MIPI1_PIXEL_CLK				108
-#define IMX_MIPI1_BYPASS_CLK				109
-#define IMX_MIPI1_LVDS_PIXEL_CLK			110
-#define IMX_MIPI1_LVDS_BYPASS_CLK			111
-#define IMX_MIPI1_LVDS_PHY_CLK				112
-#define IMX_MIPI1_I2C0_CLK				113
-#define IMX_MIPI1_I2C1_CLK				114
-#define IMX_MIPI1_PWM0_CLK				115
-
-/* IMG SS */
-#define IMX_IMG_AXI_CLK					120
-#define IMX_IMG_IPG_CLK					121
-#define IMX_IMG_PXL_CLK					122
-
-/* MIPI-CSI SS */
-#define IMX_CSI0_CORE_CLK				130
-#define IMX_CSI0_ESC_CLK				131
-#define IMX_CSI0_PWM0_CLK				132
-#define IMX_CSI0_I2C0_CLK				133
-
-/* PARALLER CSI SS */
-#define IMX_PARALLEL_CSI_DPLL_CLK			140
-#define IMX_PARALLEL_CSI_PIXEL_CLK			141
-#define IMX_PARALLEL_CSI_MCLK_CLK			142
-
-/* VPU SS */
-#define IMX_VPU_ENC_CLK					150
-#define IMX_VPU_DEC_CLK					151
-
-/* GPU SS */
-#define IMX_GPU0_CORE_CLK				160
-#define IMX_GPU0_SHADER_CLK				161
-
-/* ADMA SS */
-#define IMX_ADMA_IPG_CLK_ROOT				165
-#define IMX_ADMA_UART0_CLK				170
-#define IMX_ADMA_UART1_CLK				171
-#define IMX_ADMA_UART2_CLK				172
-#define IMX_ADMA_UART3_CLK				173
-#define IMX_ADMA_SPI0_CLK				174
-#define IMX_ADMA_SPI1_CLK				175
-#define IMX_ADMA_SPI2_CLK				176
-#define IMX_ADMA_SPI3_CLK				177
-#define IMX_ADMA_CAN0_CLK				178
-#define IMX_ADMA_CAN1_CLK				179
-#define IMX_ADMA_CAN2_CLK				180
-#define IMX_ADMA_I2C0_CLK				181
-#define IMX_ADMA_I2C1_CLK				182
-#define IMX_ADMA_I2C2_CLK				183
-#define IMX_ADMA_I2C3_CLK				184
-#define IMX_ADMA_FTM0_CLK				185
-#define IMX_ADMA_FTM1_CLK				186
-#define IMX_ADMA_ADC0_CLK				187
-#define IMX_ADMA_PWM_CLK				188
-#define IMX_ADMA_LCD_CLK				189
-
-#define IMX_SCU_CLK_END					190
-
-/* LPCG clocks */
-
-/* LSIO SS LPCG */
-#define IMX_LSIO_LPCG_PWM0_IPG_CLK			0
-#define IMX_LSIO_LPCG_PWM0_IPG_S_CLK			1
-#define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK			2
-#define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK			3
-#define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK			4
-#define IMX_LSIO_LPCG_PWM1_IPG_CLK			5
-#define IMX_LSIO_LPCG_PWM1_IPG_S_CLK			6
-#define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK			7
-#define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK			8
-#define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK			9
-#define IMX_LSIO_LPCG_PWM2_IPG_CLK			10
-#define IMX_LSIO_LPCG_PWM2_IPG_S_CLK			11
-#define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK			12
-#define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK			13
-#define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK			14
-#define IMX_LSIO_LPCG_PWM3_IPG_CLK			15
-#define IMX_LSIO_LPCG_PWM3_IPG_S_CLK			16
-#define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK			17
-#define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK			18
-#define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK			19
-#define IMX_LSIO_LPCG_PWM4_IPG_CLK			20
-#define IMX_LSIO_LPCG_PWM4_IPG_S_CLK			21
-#define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK			22
-#define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK			23
-#define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK			24
-#define IMX_LSIO_LPCG_PWM5_IPG_CLK			25
-#define IMX_LSIO_LPCG_PWM5_IPG_S_CLK			26
-#define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK			27
-#define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK			28
-#define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK			29
-#define IMX_LSIO_LPCG_PWM6_IPG_CLK			30
-#define IMX_LSIO_LPCG_PWM6_IPG_S_CLK			31
-#define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK			32
-#define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK			33
-#define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK			34
-#define IMX_LSIO_LPCG_PWM7_IPG_CLK			35
-#define IMX_LSIO_LPCG_PWM7_IPG_S_CLK			36
-#define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK			37
-#define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK			38
-#define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK			39
-#define IMX_LSIO_LPCG_GPT0_IPG_CLK			40
-#define IMX_LSIO_LPCG_GPT0_IPG_S_CLK			41
-#define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK			42
-#define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK			43
-#define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK			44
-#define IMX_LSIO_LPCG_GPT1_IPG_CLK			45
-#define IMX_LSIO_LPCG_GPT1_IPG_S_CLK			46
-#define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK			47
-#define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK			48
-#define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK			49
-#define IMX_LSIO_LPCG_GPT2_IPG_CLK			50
-#define IMX_LSIO_LPCG_GPT2_IPG_S_CLK			51
-#define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK			52
-#define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK			53
-#define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK			54
-#define IMX_LSIO_LPCG_GPT3_IPG_CLK			55
-#define IMX_LSIO_LPCG_GPT3_IPG_S_CLK			56
-#define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK			57
-#define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK			58
-#define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK			59
-#define IMX_LSIO_LPCG_GPT4_IPG_CLK			60
-#define IMX_LSIO_LPCG_GPT4_IPG_S_CLK			61
-#define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK			62
-#define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK			63
-#define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK			64
-#define IMX_LSIO_LPCG_FSPI0_HCLK			65
-#define IMX_LSIO_LPCG_FSPI0_IPG_CLK			66
-#define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK			67
-#define IMX_LSIO_LPCG_FSPI0_IPG_SFCK			68
-#define IMX_LSIO_LPCG_FSPI1_HCLK			69
-#define IMX_LSIO_LPCG_FSPI1_IPG_CLK			70
-#define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK			71
-#define IMX_LSIO_LPCG_FSPI1_IPG_SFCK			72
-
-#define IMX_LSIO_LPCG_CLK_END				73
-
-/* Connectivity SS LPCG */
-#define IMX_CONN_LPCG_SDHC0_IPG_CLK			0
-#define IMX_CONN_LPCG_SDHC0_PER_CLK			1
-#define IMX_CONN_LPCG_SDHC0_HCLK			2
-#define IMX_CONN_LPCG_SDHC1_IPG_CLK			3
-#define IMX_CONN_LPCG_SDHC1_PER_CLK			4
-#define IMX_CONN_LPCG_SDHC1_HCLK			5
-#define IMX_CONN_LPCG_SDHC2_IPG_CLK			6
-#define IMX_CONN_LPCG_SDHC2_PER_CLK			7
-#define IMX_CONN_LPCG_SDHC2_HCLK			8
-#define IMX_CONN_LPCG_GPMI_APB_CLK			9
-#define IMX_CONN_LPCG_GPMI_BCH_APB_CLK			10
-#define IMX_CONN_LPCG_GPMI_BCH_IO_CLK			11
-#define IMX_CONN_LPCG_GPMI_BCH_CLK			12
-#define IMX_CONN_LPCG_APBHDMA_CLK			13
-#define IMX_CONN_LPCG_ENET0_ROOT_CLK			14
-#define IMX_CONN_LPCG_ENET0_TX_CLK			15
-#define IMX_CONN_LPCG_ENET0_AHB_CLK			16
-#define IMX_CONN_LPCG_ENET0_IPG_S_CLK			17
-#define IMX_CONN_LPCG_ENET0_IPG_CLK			18
-
-#define IMX_CONN_LPCG_ENET1_ROOT_CLK			19
-#define IMX_CONN_LPCG_ENET1_TX_CLK			20
-#define IMX_CONN_LPCG_ENET1_AHB_CLK			21
-#define IMX_CONN_LPCG_ENET1_IPG_S_CLK			22
-#define IMX_CONN_LPCG_ENET1_IPG_CLK			23
-
-#define IMX_CONN_LPCG_CLK_END				24
-
-/* ADMA SS LPCG */
-#define IMX_ADMA_LPCG_UART0_IPG_CLK			0
-#define IMX_ADMA_LPCG_UART0_BAUD_CLK			1
-#define IMX_ADMA_LPCG_UART1_IPG_CLK			2
-#define IMX_ADMA_LPCG_UART1_BAUD_CLK			3
-#define IMX_ADMA_LPCG_UART2_IPG_CLK			4
-#define IMX_ADMA_LPCG_UART2_BAUD_CLK			5
-#define IMX_ADMA_LPCG_UART3_IPG_CLK			6
-#define IMX_ADMA_LPCG_UART3_BAUD_CLK			7
-#define IMX_ADMA_LPCG_SPI0_IPG_CLK			8
-#define IMX_ADMA_LPCG_SPI1_IPG_CLK			9
-#define IMX_ADMA_LPCG_SPI2_IPG_CLK			10
-#define IMX_ADMA_LPCG_SPI3_IPG_CLK			11
-#define IMX_ADMA_LPCG_SPI0_CLK				12
-#define IMX_ADMA_LPCG_SPI1_CLK				13
-#define IMX_ADMA_LPCG_SPI2_CLK				14
-#define IMX_ADMA_LPCG_SPI3_CLK				15
-#define IMX_ADMA_LPCG_CAN0_IPG_CLK			16
-#define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK			17
-#define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK			18
-#define IMX_ADMA_LPCG_CAN1_IPG_CLK			19
-#define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK			20
-#define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK			21
-#define IMX_ADMA_LPCG_CAN2_IPG_CLK			22
-#define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK			23
-#define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK			24
-#define IMX_ADMA_LPCG_I2C0_CLK				25
-#define IMX_ADMA_LPCG_I2C1_CLK				26
-#define IMX_ADMA_LPCG_I2C2_CLK				27
-#define IMX_ADMA_LPCG_I2C3_CLK				28
-#define IMX_ADMA_LPCG_I2C0_IPG_CLK			29
-#define IMX_ADMA_LPCG_I2C1_IPG_CLK			30
-#define IMX_ADMA_LPCG_I2C2_IPG_CLK			31
-#define IMX_ADMA_LPCG_I2C3_IPG_CLK			32
-#define IMX_ADMA_LPCG_FTM0_CLK				33
-#define IMX_ADMA_LPCG_FTM1_CLK				34
-#define IMX_ADMA_LPCG_FTM0_IPG_CLK			35
-#define IMX_ADMA_LPCG_FTM1_IPG_CLK			36
-#define IMX_ADMA_LPCG_PWM_HI_CLK			37
-#define IMX_ADMA_LPCG_PWM_IPG_CLK			38
-#define IMX_ADMA_LPCG_LCD_PIX_CLK			39
-#define IMX_ADMA_LPCG_LCD_APB_CLK			40
-#define IMX_ADMA_LPCG_DSP_ADB_CLK			41
-#define IMX_ADMA_LPCG_DSP_IPG_CLK			42
-#define IMX_ADMA_LPCG_DSP_CORE_CLK			43
-#define IMX_ADMA_LPCG_OCRAM_IPG_CLK			44
-
-#define IMX_ADMA_LPCG_CLK_END				45
+#define IMX_ADMA_ACM_AUD_CLK0_SEL			0
+#define IMX_ADMA_ACM_AUD_CLK0_CLK			1
+#define IMX_ADMA_ACM_AUD_CLK1_SEL			2
+#define IMX_ADMA_ACM_AUD_CLK1_CLK			3
+#define IMX_ADMA_ACM_MCLKOUT0_SEL			4
+#define IMX_ADMA_ACM_MCLKOUT1_SEL			5
+#define IMX_ADMA_ACM_ESAI0_MCLK_SEL			6
+#define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL			7
+#define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL			8
+#define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL			9
+#define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL			10
+#define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL			11
+#define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL			12
+#define IMX_ADMA_ACM_SAI0_MCLK_SEL			13
+#define IMX_ADMA_ACM_SAI1_MCLK_SEL			14
+#define IMX_ADMA_ACM_SAI2_MCLK_SEL			15
+#define IMX_ADMA_ACM_SAI3_MCLK_SEL			16
+#define IMX_ADMA_ACM_SAI4_MCLK_SEL			17
+#define IMX_ADMA_ACM_SAI5_MCLK_SEL			18
+#define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL			19
+#define IMX_ADMA_ACM_MQS_TX_CLK_SEL			20
+#define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL			21
+#define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL			22
+
+#define IMX_ADMA_EXT_AUD_MCLK0				23
+#define IMX_ADMA_EXT_AUD_MCLK1				24
+#define IMX_ADMA_ESAI0_RX_CLK				25
+#define IMX_ADMA_ESAI0_RX_HF_CLK			26
+#define IMX_ADMA_ESAI0_TX_CLK				27
+#define IMX_ADMA_ESAI0_TX_HF_CLK			28
+#define IMX_ADMA_SPDIF0_RX				29
+#define IMX_ADMA_SAI0_RX_BCLK				30
+#define IMX_ADMA_SAI0_TX_BCLK				31
+#define IMX_ADMA_SAI1_RX_BCLK				32
+#define IMX_ADMA_SAI1_TX_BCLK				33
+#define IMX_ADMA_SAI2_RX_BCLK				34
+#define IMX_ADMA_SAI3_RX_BCLK				35
+#define IMX_ADMA_SAI4_RX_BCLK				36
+#define IMX_ADMA_SAI5_TX_BCLK				37
+#define IMX_ADMA_SAI6_RX_BCLK				38
+#define IMX_ADMA_HDMI_RX_MCLK				39
+#define IMX_ADMA_MLB_CLK				40
+#define IMX_ADMA_SPDIF1_RX				41
+#define IMX_ADMA_ESAI1_RX_CLK				42
+#define IMX_ADMA_ESAI1_RX_HF_CLK			43
+#define IMX_ADMA_ESAI1_TX_CLK				44
+#define IMX_ADMA_ESAI1_TX_HF_CLK			45
+
+#define IMX_ADMA_ACM_ESAI1_MCLK_SEL			46
+#define IMX_ADMA_ACM_SAI6_MCLK_SEL			47
+#define IMX_ADMA_ACM_SAI7_MCLK_SEL			48
+#define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL			49
+
+#define IMX_ADMA_ACM_CLK_END				50
 
 #endif /* __DT_BINDINGS_CLOCK_IMX_H */
diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h
index 65463673d25e..ee2eb2bef7c1 100644
--- a/include/dt-bindings/clock/imx8mq-clock.h
+++ b/include/dt-bindings/clock/imx8mq-clock.h
@@ -403,5 +403,9 @@
 #define IMX8MQ_CLK_SNVS_ROOT			264
 #define IMX8MQ_CLK_GIC				265
 
-#define IMX8MQ_CLK_END				266
+#define IMX8MQ_VIDEO2_PLL1_REF_SEL		266
+
+#define IMX8MQ_CLK_PHY_27MHZ			267
+
+#define IMX8MQ_CLK_END				268
 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
diff --git a/include/dt-bindings/clock/s32v234-clock.h b/include/dt-bindings/clock/s32v234-clock.h
new file mode 100644
index 000000000000..1ddfae5c1422
--- /dev/null
+++ b/include/dt-bindings/clock/s32v234-clock.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright (C) 2017 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S32V234_H
+#define __DT_BINDINGS_CLOCK_S32V234_H
+
+#define	S32V234_CLK_DUMMY			0
+#define	S32V234_CLK_FXOSC			1
+#define	S32V234_CLK_FIRC			2
+/* PERIPH PLL */
+#define	S32V234_CLK_PERIPHPLL_SRC_SEL		3
+#define	S32V234_CLK_PERIPHPLL_VCO		4
+#define	S32V234_CLK_PERIPHPLL_PHI0		5
+#define	S32V234_CLK_PERIPHPLL_PHI0_DIV3		6
+#define	S32V234_CLK_PERIPHPLL_PHI0_DIV5		7
+#define	S32V234_CLK_PERIPHPLL_PHI1		8
+/* LINFlexD Clock */
+#define	S32V234_CLK_LIN				9
+#define	S32V234_CLK_LIN_SEL			10
+#define	S32V234_CLK_LIN_IPG			11
+/* SDHC Clock */
+#define	S32V234_CLK_SDHC			12
+#define	S32V234_CLK_SDHC_SEL			13
+/* ENET PLL */
+#define	S32V234_CLK_ENETPLL_SRC_SEL		14
+#define	S32V234_CLK_ENETPLL_VCO			15
+#define	S32V234_CLK_ENETPLL_PHI0		16
+#define	S32V234_CLK_ENETPLL_PHI1		17
+#define	S32V234_CLK_ENETPLL_DFS0		18
+#define	S32V234_CLK_ENETPLL_DFS1		19
+#define	S32V234_CLK_ENETPLL_DFS2		20
+#define	S32V234_CLK_ENETPLL_DFS3		21
+/* System Clock */
+#define	S32V234_CLK_SYS_SEL			22
+#define	S32V234_CLK_SYS3			23
+#define	S32V234_CLK_SYS6			24
+#define	S32V234_CLK_SYS6_DIV2			25
+/* ENET Clock */
+#define	S32V234_CLK_ENET_TIME_DIV		26
+#define	S32V234_CLK_ENET_TIME_SEL		27
+#define	S32V234_CLK_ENET_DIV			28
+#define	S32V234_CLK_ENET_SEL			29
+
+#define	S32V234_CLK_ENET			30
+#define	S32V234_CLK_ENET_TIME			31
+
+/* ARM PLL */
+#define	S32V234_CLK_ARMPLL_SRC_SEL		32
+#define	S32V234_CLK_ARMPLL_VCO			33
+#define	S32V234_CLK_ARMPLL_PHI0			34
+#define	S32V234_CLK_ARMPLL_PHI1			35
+#define	S32V234_CLK_ARMPLL_DFS0			35
+#define	S32V234_CLK_ARMPLL_DFS1			36
+#define	S32V234_CLK_ARMPLL_DFS2			37
+
+/* CAN Clock */
+#define S32V234_CLK_CAN				38
+#define S32V234_CLK_CAN_SEL			39
+
+#define	S32V234_CLK_END				40
+
+#endif /* __DT_BINDINGS_CLOCK_S32V234_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 2fdfe8061363..30b61ec0e167 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -32,6 +32,7 @@
 #define CLK_OPS_PARENT_ENABLE	BIT(12)
 /* duty cycle call may be forwarded to the parent clock */
 #define CLK_DUTY_CYCLE_PARENT	BIT(13)
+#define CLK_SET_PARENT_NOCACHE	BIT(14) /* do not use the cached clk parent */
 
 struct clk;
 struct clk_hw;
diff --git a/include/soc/imx/gpc.h b/include/soc/imx/gpc.h
new file mode 100644
index 000000000000..6a976e6aa3fe
--- /dev/null
+++ b/include/soc/imx/gpc.h
@@ -0,0 +1,7 @@
+#ifndef __SOC_IMX_GPC_H
+#define __SOC_IMX_GPC_H
+
+void imx_gpc_hold_m4_in_sleep(void);
+void imx_gpc_release_m4_in_sleep(void);
+
+#endif /* __SOC_IMX_GPC_H */
diff --git a/include/soc/imx/src.h b/include/soc/imx/src.h
new file mode 100644
index 000000000000..c55c34cd2366
--- /dev/null
+++ b/include/soc/imx/src.h
@@ -0,0 +1,6 @@
+#ifndef __SOC_IMX_SRC_H
+#define __SOC_IMX_SRC_H
+
+bool imx_src_is_m4_enabled(void);
+
+#endif /* __SOC_IMX_SRC_H */