diff options
| author | Michael Buesch <mb@bu3sch.de> | 2008-02-18 21:44:39 +0100 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2008-02-20 20:11:48 -0500 |
| commit | 58ff70d4feae29cbb7ace410fa6585ef3afb44b6 (patch) | |
| tree | 298ddfd64df8fbab670538202f93cf0bc028605a /include | |
| parent | 04f93a87a2db84e7214a4ec56fccd2289e973ce5 (diff) | |
ssb: Fix serial console on new bcm47xx devices
This fixes the baud settings for new devices
like the Linksys WRT350n.
Signed-off-by: Michael Buesch <mb@bu3sch.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/ssb/ssb_driver_chipcommon.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/linux/ssb/ssb_driver_chipcommon.h b/include/linux/ssb/ssb_driver_chipcommon.h index 4cb995494662..35717b400cef 100644 --- a/include/linux/ssb/ssb_driver_chipcommon.h +++ b/include/linux/ssb/ssb_driver_chipcommon.h @@ -51,9 +51,12 @@ #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ +#define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ +#define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ #define SSB_CHIPCO_CORECTL 0x0008 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ +#define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ #define SSB_CHIPCO_BIST 0x000C #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 |