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authorSinthu Raja <sinthu.raja@ti.com>2023-01-18 17:08:15 +0530
committerVignesh Raghavendra <vigneshr@ti.com>2023-01-19 15:51:43 +0530
commit1007a3d40f26f41df113ada48d1fa1a0ba822fa4 (patch)
tree870e4333b8aea028b610ebb4f5839378beafe11c /include
parent200d21652fae5420e2cb6b6f9312783540ef41f9 (diff)
dt-bindings: ti-serdes-mux: Add USB Type C swap defines for J721S2 SoC
Lanes 0 and 2 of the J721S2 SerDes WIZ are reserved for USB type-C lane swap if Lanes 1 and 3 are connected to the SerDes IP's USB PHY. Remove the defines that state the Lane 0 and Lane 2 IPs are unused, and instead define the Type C swap configuration macro. Signed-off-by: Sinthu Raja <sinthu.raja@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'include')
-rw-r--r--include/dt-bindings/mux/ti-serdes.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
index 669ca2d6abce..91ea9633c00c 100644
--- a/include/dt-bindings/mux/ti-serdes.h
+++ b/include/dt-bindings/mux/ti-serdes.h
@@ -99,7 +99,7 @@
#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0
#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1
-#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE0_USB_SWAP 0x2
#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0
@@ -109,7 +109,7 @@
#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0
#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1
-#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2
+#define J721S2_SERDES0_LANE2_USB_SWAP 0x2
#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3
#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0