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authorBibek Basu <bbasu@nvidia.com>2014-11-06 16:34:09 +0530
committerWinnie Hsu <whsu@nvidia.com>2014-11-21 13:46:32 -0800
commite9b32d4342a9ee9308729ae0c725d421869a0538 (patch)
treeb75923e1184e8620e4a7e8650b306fb96d606d9c /include
parent2c1ad0be0a4ef9a83f8fbdbb19dbc72cb83f7420 (diff)
arm: tegra12: add support for CD575M 24x7 Chip
Added DVFS support for CD575M Always on behaviour. With this personality configuration for the chip,the lifetime of the chip increases to 5 Yrs Operating Temp : -25 to 105 degC CPU DVFS: Max Freq 1938Mhz. Max Voltage 1.12V SOC DVFS: Max Voltage0 1.01V EMC dvfs max freq 792Mhz GPU DVFS: Max Freq 804Mhz and Ma Voltage 1.09V Bug 1563635 Change-Id: If7fec38b83ae4de8c5435006207fa3cf717384c0 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/594855 GVS: Gerrit_Virtual_Submit Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/clk/tegra.h1
-rw-r--r--include/linux/tegra-fuse.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 2a374c56297d..8394de40787c 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -168,6 +168,7 @@ void tegra_unregister_clk_rate_notifier(
struct clk *c, struct notifier_block *nb);
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
int tegra_dvfs_use_alt_freqs_on_clk(struct clk *c, bool use_alt_freq);
+unsigned long clk_get_max_rate(struct clk *c);
/**
* tegra_is_clk_enabled - get info if the clk is enabled or not
diff --git a/include/linux/tegra-fuse.h b/include/linux/tegra-fuse.h
index c12770eafcf5..0d2b9c967bce 100644
--- a/include/linux/tegra-fuse.h
+++ b/include/linux/tegra-fuse.h
@@ -60,6 +60,7 @@ int tegra_core_speedo_mv(void);
int tegra_gpu_speedo_id(void);
int tegra_get_sku_override(void);
int tegra_get_cpu_iddq_value(void);
+int tegra_get_chip_personality(void);
#ifdef CONFIG_ARCH_TEGRA_12x_SOC
int tegra_cpu_speedo_0_value(void);