diff options
| author | Pradeep Goudagunta <pgoudagunta@nvidia.com> | 2011-03-28 16:32:40 +0530 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-03-28 23:49:40 -0700 |
| commit | 66fa9abefccdc75f6feb283ac60acacd257dcc99 (patch) | |
| tree | df53d1ee1bf5a6c5cb1f75c986ee5da537b2469c /include | |
| parent | 0b59165a49eec6bf9bda100ee7b9bca988ac89b8 (diff) | |
serial: 8250: support auto control of RTSCTS on tegra type
Add UART_CAP_HW_CTSRTS flag to tegra type for supporting auto control
of RTSCTS.
Bug 803910
Change-Id: I7b69e4b203e66903ba5755338fcb55f4a87b9a43
Reviewed-on: http://git-master/r/24463
Tested-by: Pradeep Goudagunta <pgoudagunta@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/serial_reg.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index c7a0ce11cd47..0d80447f99be 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -2,10 +2,10 @@ * include/linux/serial_reg.h * * Copyright (C) 1992, 1994 by Theodore Ts'o. - * - * Redistribution of this file is permitted under the terms of the GNU + * + * Redistribution of this file is permitted under the terms of the GNU * Public License (GPL) - * + * * These are the UART port assignments, expressed as offsets from the base * register. These assignments should hold for any serial port based on * a 8250, 16450, or 16550(A). @@ -85,7 +85,7 @@ #define UART_LCR 3 /* Out: Line Control Register */ /* - * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. */ #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ @@ -102,8 +102,10 @@ #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ +#define UART_MCR_HW_RTS 0x40 /* Enable hw control of RTS (Tegra UART) */ #define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ +#define UART_MCR_HW_CTS 0x20 /* Enable HW based CTS control (Tegra UART)*/ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ #define UART_MCR_OUT2 0x08 /* Out2 complement */ #define UART_MCR_OUT1 0x04 /* Out1 complement */ |