misc: tegra-profiler: squashed update to ver. 1.75

commit f8c056c12c7b72290c47afadaf8b2f16336b3238
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Thu Jun 5 11:57:52 2014 +0400

    misc: tegra-profiler: mixed backtraces

    Unwinding: switch from code with frame pointers to code
    with unwind tables.

    Bug 1487488

    Change-Id: I254a8fd762b5312f854db1fe79635a2b419091f0
    Reviewed-on: http://git-master/r/419384

commit a1d7f98fb15d4578cd140fe03a4c748e1db86c57
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Thu Jun 5 11:08:55 2014 +0400

    misc: tegra-profiler: add sched samples

    Tegra Profiler: capture task starting being scheduled on a core.
    Add sched in/out samples.

    Bug 1520808

    Change-Id: I2c62e5c1918bdba0fc997d79d8aeb3b7b63530f0
    Reviewed-on: http://git-master/r/419352

commit 6f847fd1257af28fc11b942a2f3b3dfc7eb4579f
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Thu Jun 5 09:52:29 2014 +0400

    misc: tegra-profiler: use cntvct as time source

    Tegra Profiler: use Virtual Count register (CNTVCT) as
    time source.

    Bug 1508327

    Change-Id: If37e2dbe0a256ec28575d7c1b7d601d6bc1090f5
    Reviewed-on: http://git-master/r/419305

commit d79e4f5292dae4cccb510be2b47f4ee00baa53d7
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Thu Jun 5 09:10:47 2014 +0400

    misc: tegra-profiler: get perfmon extension

    Add version of the ARMv8 NVIDIA perfmon extension to
    device capabilities.

    Bug 1520757

    Change-Id: I18d10133272a10e3faf5022b4579c7dfea78791e
    Reviewed-on: http://git-master/r/419274

commit afedef10f26475b98b7d42ab3bab6f0c2fbb6eae
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Mon May 19 16:49:19 2014 +0400

    misc: tegra-profiler: fix hang up bug for Norrin

    Do not use probe_kernel_address.
    Actually, it is not safe on Norrin: this can lead to system crash.

    Bug 200005974
    Bug 1522252

    Change-Id: If8bae9afd7c7e1bbb5beaf430c0c61f552aeb036
    Reviewed-on: http://git-master/r/411507

commit 1b4c5247c0ab284dbed25683cbfa5a301da787ff
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Fri May 16 12:49:15 2014 +0400

    misc: tegra-profiler: add unwind information

    Tegra Profiler: add additional unwind information
    for each call entry.

    Bug 1514626

    Change-Id: I2873941a4c903e0e7e909897ead55eb34d80b966
    Reviewed-on: http://git-master/r/410770

commit b2f593d9bb00a380d4402f2a8cd9ed8d9646dcbd
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Fri May 16 12:05:36 2014 +0400

    misc: tegra-profiler: fixed recursive call chains

    In some cases, recursive call chains can be broken.
    This patch fixes this problem.

    Bug 200005395

    Change-Id: I7d31ec64b004109c3684cf0d143d9b1d6cd59f9f
    Reviewed-on: http://git-master/r/410745

commit 6c9f626340a81daf124d4bbeff2254f63cc084b7
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Fri May 16 11:24:50 2014 +0400

    misc: tegra-profiler: support too deep stack level

    Too deep stack level: handle it properly.
    Appropriate unwind reason code has been added.

    Unwinding based on frame pointers: add unwind reason codes.

    Bug 200005380

    Change-Id: I2199df90c746ada6a7f224a8b675638b69dc6da8
    Reviewed-on: http://git-master/r/410717

commit ddea2fc86588bdf3ae313a270364052a0beab160
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Fri May 16 10:44:06 2014 +0400

    misc: tegra-profiler: fix setup bug

    * Fix bug that happens when using non-standard profiling frequencies
    * Allow root user to use any frequency in range [100 Hz; 100 kHz]

    Bug 200005366

    Change-Id: I9a07e2c9c1fec6d61f34009d1975ea7f5d0e2592
    Reviewed-on: http://git-master/r/410705

commit 5c64bcefc4b3df0ba9612cd67703593d488ab38c
Author: Deepak Nibade <dnibade@nvidia.com>
Date:   Mon May 19 15:48:02 2014 +0530

    misc: tegra-profiler: fix resource leaks

    Fix Coverity issue of resource leaks
    Coverity id : 26481
    Coverity id : 26483

    Bug 1416640

    Change-Id: Ib71950f196b5421ccbc21b3ac8d620e790e83366
    Reviewed-on: http://git-master/r/411421

commit 2f5d99b96ba18129f6c708e3db9a1e32da24816f
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Tue May 6 09:47:02 2014 +0400

    tegra-profiler: add access to the exception tables

    Tegra Profiler: add access to the exception tables via mmap areas.
    Do not read directly from the user space.

    Bug 200002243

    Change-Id: I442daaecb11fd4416b3e485722efdf34234e0241
    Reviewed-on: http://git-master/r/405671

commit 218d8cc8a573da49145c7104258fb290c83205b9
Author: Igor Nabirushkin <inabirushkin@nvidia.com>
Date:   Thu Apr 17 13:02:07 2014 +0400

    misc: tegra-profiler: unwinding: use RCU locking

    Unwinding: use RCU locking instead of spinlocks to protect
    map of regions.

    Bug 1502205

    Change-Id: If1089b74b1f317eeaae5059de40d7a3365ae4061
    Reviewed-on: http://git-master/r/397599

Change-Id: I1ac2a5a290f723cab40463932c0a814a670cf9e7
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/424787
GVS: Gerrit_Virtual_Submit
Tested-by: Daniel Horowitz <dhorowitz@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 44 insertions, 2 deletions

diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h
index f1d47520cfd9..3ba50b60b342 100644
--- a/include/linux/tegra_profiler.h
+++ b/include/linux/tegra_profiler.h
@@ -19,8 +19,8 @@
 
 #include <linux/ioctl.h>
 
-#define QUADD_SAMPLES_VERSION	25
-#define QUADD_IO_VERSION	11
+#define QUADD_SAMPLES_VERSION	29
+#define QUADD_IO_VERSION	12
 
 #define QUADD_IO_VERSION_DYNAMIC_RB		5
 #define QUADD_IO_VERSION_RB_MAX_FILL_COUNT	6
@@ -29,6 +29,7 @@
 #define QUADD_IO_VERSION_GET_MMAP		9
 #define QUADD_IO_VERSION_BT_UNWIND_TABLES	10
 #define QUADD_IO_VERSION_UNWIND_MIXED		11
+#define QUADD_IO_VERSION_EXTABLES_MMAP		12
 
 #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG	17
 #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES	18
@@ -37,6 +38,10 @@
 #define QUADD_SAMPLE_VERSION_SUPPORT_IP64	23
 #define QUADD_SAMPLE_VERSION_SPECIAL_MMAP	24
 #define QUADD_SAMPLE_VERSION_UNWIND_MIXED	25
+#define QUADD_SAMPLE_VERSION_UNW_ENTRY_TYPE	26
+#define QUADD_SAMPLE_VERSION_USE_ARCH_TIMER	27
+#define QUADD_SAMPLE_VERSION_SCHED_SAMPLES	28
+#define QUADD_SAMPLE_VERSION_HDR_UNW_METHOD	29
 
 #define QUADD_MAX_COUNTERS	32
 #define QUADD_MAX_PROCESS	64
@@ -123,6 +128,7 @@ enum quadd_record_type {
 	QUADD_RECORD_TYPE_HEADER,
 	QUADD_RECORD_TYPE_POWER_RATE,
 	QUADD_RECORD_TYPE_ADDITIONAL_SAMPLE,
+	QUADD_RECORD_TYPE_SCHED,
 };
 
 enum quadd_event_source {
@@ -145,6 +151,7 @@ enum {
 	QUADD_UNW_METHOD_FP = 0,
 	QUADD_UNW_METHOD_EHT,
 	QUADD_UNW_METHOD_MIXED,
+	QUADD_UNW_METHOD_NONE,
 };
 
 #define QUADD_SAMPLE_URC_SHIFT		1
@@ -164,6 +171,9 @@ enum {
 	QUADD_URC_SPARE_ENCODING,
 	QUADD_URC_UNSUPPORTED_PR,
 	QUADD_URC_PC_INCORRECT,
+	QUADD_URC_LEVEL_TOO_DEEP,
+	QUADD_URC_FP_INCORRECT,
+	QUADD_URC_MAX,
 };
 
 #define QUADD_SED_IP64			(1 << 0)
@@ -171,6 +181,14 @@ enum {
 #define QUADD_SED_UNW_METHOD_SHIFT	1
 #define QUADD_SED_UNW_METHOD_MASK	(0x07 << QUADD_SED_UNW_METHOD_SHIFT)
 
+enum {
+	QUADD_UNW_TYPE_FP = 0,
+	QUADD_UNW_TYPE_UT,
+	QUADD_UNW_TYPE_LR_FP,
+	QUADD_UNW_TYPE_LR_UT,
+	QUADD_UNW_TYPE_KCTX,
+};
+
 struct quadd_sample_data {
 	u64 ip;
 	u32 pid;
@@ -224,6 +242,18 @@ struct quadd_additional_sample {
 	u16 extra_length;
 };
 
+struct quadd_sched_data {
+	u32 pid;
+	u64 time;
+
+	u32	cpu:6,
+		lp_mode:1,
+		sched_in:1,
+		reserved:24;
+
+	u32 data[2];
+};
+
 enum {
 	QM_DEBUG_SAMPLE_TYPE_SCHED_IN = 1,
 	QM_DEBUG_SAMPLE_TYPE_SCHED_OUT,
@@ -257,6 +287,9 @@ struct quadd_debug_data {
 
 #define QUADD_HEADER_MAGIC	0x1122
 
+#define QUADD_HDR_UNW_METHOD_SHIFT	0
+#define QUADD_HDR_UNW_METHOD_MASK	(0x07 << QUADD_HDR_UNW_METHOD_SHIFT)
+
 struct quadd_header_data {
 	u16 magic;
 	u16 version;
@@ -288,6 +321,7 @@ struct quadd_record_data {
 		struct quadd_debug_data		debug;
 		struct quadd_header_data	hdr;
 		struct quadd_power_rate_data	power_rate;
+		struct quadd_sched_data		sched;
 		struct quadd_additional_sample	additional_sample;
 	};
 } __aligned(4);
@@ -354,6 +388,8 @@ enum {
 #define QUADD_COMM_CAP_EXTRA_SUPPORT_AARCH64	(1 << 4)
 #define QUADD_COMM_CAP_EXTRA_SPECIAL_ARCH_MMAP	(1 << 5)
 #define QUADD_COMM_CAP_EXTRA_UNWIND_MIXED	(1 << 6)
+#define QUADD_COMM_CAP_EXTRA_UNW_ENTRY_TYPE	(1 << 7)
+#define QUADD_COMM_CAP_EXTRA_USE_ARCH_TIMER	(1 << 8)
 
 struct quadd_comm_cap {
 	u32	pmu:1,
@@ -401,6 +437,12 @@ struct quadd_sec_info {
 	u64 length;
 };
 
+enum {
+	QUADD_EXT_IDX_EXTAB_OFFSET = 0,
+	QUADD_EXT_IDX_EXIDX_OFFSET = 1,
+	QUADD_EXT_IDX_MMAP_VM_START = 2,
+};
+
 struct quadd_extables {
 	u64 vm_start;
 	u64 vm_end;