Merge branch 'l4t/l4t-r16-r2' into colibri

Conflicts:
	arch/arm/mach-tegra/tegra3_usb_phy.c
	arch/arm/mach-tegra/usb_phy.c
	drivers/usb/gadget/tegra_udc.c
	drivers/usb/otg/Makefile
	drivers/video/tegra/fb.c
	sound/soc/tegra/tegra_pcm.c

31 files changed, 1176 insertions, 104 deletions

diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index 54d948ec49ab..d732be526293 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -66,8 +66,9 @@ enum {
 	/* migration should happen before other stuff but after perf */
 	CPU_PRI_PERF		= 20,
 	CPU_PRI_MIGRATION	= 10,
-	/* prepare workqueues for other notifiers */
-	CPU_PRI_WORKQUEUE	= 5,
+	/* bring up workqueues before normal notifiers and down after */
+	CPU_PRI_WORKQUEUE_UP	= 5,
+	CPU_PRI_WORKQUEUE_DOWN	= -5,
 };
 
 #define CPU_ONLINE		0x0002 /* CPU (unsigned)v is up */
diff --git a/include/linux/cpuquiet.h b/include/linux/cpuquiet.h
index fe5a03727739..5558c015bb50 100644
--- a/include/linux/cpuquiet.h
+++ b/include/linux/cpuquiet.h
@@ -30,6 +30,8 @@ struct cpuquiet_governor {
 	int (*start)		(void);
 	void (*stop)		(void);
 	int (*store_active)	(unsigned int cpu, bool active);
+	void (*device_free_notification) (void);
+	void (*device_busy_notification) (void);
 	struct module		*owner;
 };
 
@@ -47,6 +49,8 @@ extern int cpuquiet_register_driver(struct cpuquiet_driver *drv);
 extern void cpuquiet_unregister_driver(struct cpuquiet_driver *drv);
 extern int cpuquiet_add_group(struct attribute_group *attrs);
 extern void cpuquiet_remove_group(struct attribute_group *attrs);
+extern void cpuquiet_device_busy(void);
+extern void cpuquiet_device_free(void);
 int cpuquiet_kobject_init(struct kobject *kobj, struct kobj_type *type,
 				char *name);
 extern unsigned int nr_cluster_ids;
diff --git a/include/linux/mfd/max77665.h b/include/linux/mfd/max77665.h
new file mode 100644
index 000000000000..380a1a4aac0d
--- /dev/null
+++ b/include/linux/mfd/max77665.h
@@ -0,0 +1,92 @@
+/*
+ * Core driver interface for MAXIM77665
+ *
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_MFD_MAX77665_H
+#define __LINUX_MFD_MAX77665_H
+
+#include <linux/irq.h>
+#include <linux/regmap.h>
+
+/* MAX77665 Interrups */
+enum {
+	MAX77665_IRQ_CHARGER,
+	MAX77665_IRQ_TOP_SYS,
+	MAX77665_IRQ_FLASH,
+	MAX77665_IRQ_MUIC,
+};
+
+enum {
+	MAX77665_I2C_SLAVE_PMIC,
+	MAX77665_I2C_SLAVE_MUIC,
+	MAX77665_I2C_SLAVE_HAPTIC,
+	MAX77665_I2C_SLAVE_MAX,
+};
+
+struct max77665 {
+	struct device		*dev;
+	struct i2c_client	*client[MAX77665_I2C_SLAVE_MAX];
+	struct regmap		*regmap[MAX77665_I2C_SLAVE_MAX];
+	struct irq_chip		irq_chip;
+	struct mutex		irq_lock;
+	int			irq_base;
+};
+
+struct max77665_platform_data {
+	int irq_base;
+};
+
+static inline int max77665_write(struct device *dev, int slv_id,
+		int reg, uint8_t val)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+
+	return regmap_write(maxim->regmap[slv_id], reg, val);
+}
+
+static inline int max77665_read(struct device *dev, int slv_id,
+		int reg, uint8_t *val)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+	unsigned int temp_val;
+	int ret;
+
+	ret = regmap_read(maxim->regmap[slv_id], reg, &temp_val);
+	if (!ret)
+		*val = temp_val;
+	return ret;
+}
+
+static inline int max77665_set_bits(struct device *dev, int slv_id,
+		int reg, uint8_t bit_num)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+
+	return regmap_update_bits(maxim->regmap[slv_id],
+				reg, BIT(bit_num), ~0u);
+}
+
+static inline int max77665_clr_bits(struct device *dev, int slv_id,
+		int reg, uint8_t bit_num)
+{
+	struct max77665 *maxim = dev_get_drvdata(dev);
+
+	return regmap_update_bits(maxim->regmap[slv_id],
+				reg, BIT(bit_num), 0u);
+}
+
+#endif /*__LINUX_MFD_MAX77665_H */
diff --git a/include/linux/mfd/tlv320aic3262-core.h b/include/linux/mfd/tlv320aic3262-core.h
new file mode 100644
index 000000000000..3c79ae98f860
--- /dev/null
+++ b/include/linux/mfd/tlv320aic3262-core.h
@@ -0,0 +1,237 @@
+#ifndef __MFD_AIC3262_CORE_H__
+#define __MFD_AIC3262_CORE_H__
+
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+enum aic3262_type {
+	TLV320AIC3262 = 0,
+};
+
+#define AIC3262_IRQ_HEADSET_DETECT	0
+#define AIC3262_IRQ_BUTTON_PRESS	1
+#define AIC3262_IRQ_DAC_DRC		2
+#define AIC3262_IRQ_AGC_NOISE		3
+#define AIC3262_IRQ_OVER_CURRENT	4
+#define AIC3262_IRQ_OVERFLOW_EVENT	5
+#define AIC3262_IRQ_SPEAKER_OVER_TEMP	6
+
+#define AIC3262_GPIO1			7
+#define AIC3262_GPIO2			8
+#define AIC3262_GPI1			9
+#define AIC3262_GPI2			10
+#define AIC3262_GPO1			11
+
+union aic326x_reg_union {
+	struct aic326x_reg {
+		u8 offset;
+		u8 page;
+		u8 book;
+		u8 reserved;
+	} aic326x_register;
+	unsigned int aic326x_register_int;
+};
+
+/****************************             ************************************/
+
+/*
+ *****************************************************************************
+ * Structures Definitions
+ *****************************************************************************
+ */
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_setup_data |
+ *          i2c specific data setup for AIC3262.
+ * @field   unsigned short |i2c_address |
+ *          Unsigned short for i2c address.
+ *----------------------------------------------------------------------------
+ */
+struct aic3262_setup_data {
+	unsigned short i2c_address;
+};
+
+/* GPIO API */
+#define AIC3262_NUM_GPIO 5	/* include 2 GPI and 1 GPO pins */
+enum {
+	AIC3262_GPIO1_FUNC_DISABLED =		0,
+	AIC3262_GPIO1_FUNC_INPUT =		1,
+	AIC3262_GPIO1_FUNC_OUTPUT =		3,
+	AIC3262_GPIO1_FUNC_CLOCK_OUTPUT =	4,
+	AIC3262_GPIO1_FUNC_INT1_OUTPUT =	5,
+	AIC3262_GPIO1_FUNC_INT2_OUTPUT =	6,
+	AIC3262_GPIO1_FUNC_ADC_MOD_CLK_OUTPUT =	10,
+	AIC3262_GPIO1_FUNC_SAR_ADC_INTERRUPT =	12,
+	AIC3262_GPIO1_FUNC_ASI1_DATA_OUTPUT =	15,
+	AIC3262_GPIO1_FUNC_ASI1_WCLK =		16,
+	AIC3262_GPIO1_FUNC_ASI1_BCLK =		17,
+	AIC3262_GPIO1_FUNC_ASI2_WCLK =		18,
+	AIC3262_GPIO1_FUNC_ASI2_BCLK =		19,
+	AIC3262_GPIO1_FUNC_ASI3_WCLK =		20,
+	AIC3262_GPIO1_FUNC_ASI3_BCLK =		21
+};
+
+enum {
+	AIC3262_GPIO2_FUNC_DISABLED =		0,
+	AIC3262_GPIO2_FUNC_INPUT =		1,
+	AIC3262_GPIO2_FUNC_OUTPUT =		3,
+	AIC3262_GPIO2_FUNC_CLOCK_OUTPUT =	4,
+	AIC3262_GPIO2_FUNC_INT1_OUTPUT =	5,
+	AIC3262_GPIO2_FUNC_INT2_OUTPUT =	6,
+	AIC3262_GPIO2_FUNC_ADC_MOD_CLK_OUTPUT = 10,
+	AIC3262_GPIO2_FUNC_SAR_ADC_INTERRUPT =	12,
+	AIC3262_GPIO2_FUNC_ASI1_DATA_OUTPUT =	15,
+	AIC3262_GPIO2_FUNC_ASI1_WCLK =		16,
+	AIC3262_GPIO2_FUNC_ASI1_BCLK =		17,
+	AIC3262_GPIO2_FUNC_ASI2_WCLK =		18,
+	AIC3262_GPIO2_FUNC_ASI2_BCLK =		19,
+	AIC3262_GPIO2_FUNC_ASI3_WCLK =		20,
+	AIC3262_GPIO2_FUNC_ASI3_BCLK =		21
+};
+enum {
+	AIC3262_GPO1_FUNC_DISABLED =		0,
+	AIC3262_GPO1_FUNC_MSO_OUTPUT_FOR_SPI =	1,
+	AIC3262_GPO1_FUNC_GENERAL_PURPOSE_OUTPUT = 2,
+	AIC3262_GPO1_FUNC_CLOCK_OUTPUT =	3,
+	AIC3262_GPO1_FUNC_INT1_OUTPUT =	4,
+	AIC3262_GPO1_FUNC_INT2_OUTPUT =	5,
+	AIC3262_GPO1_FUNC_ADC_MOD_CLK_OUTPUT =	7,
+	AIC3262_GPO1_FUNC_SAR_ADC_INTERRUPT =	12,
+	AIC3262_GPO1_FUNC_ASI1_DATA_OUTPUT =	15,
+};
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_configs |
+ *          AIC3262 initialization data which has register offset and register
+ *          value.
+ * @field   u8 | book_no |
+ *          AIC3262 Book Number Offsets required for initialization..
+ * @field   u16 | reg_offset |
+ *          AIC3262 Register offsets required for initialization..
+ * @field   u8 | reg_val |
+ *          value to set the AIC3262 register to initialize the AIC3262.
+ *---------------------------------------------------------------------------
+ */
+struct aic3262_configs {
+	u8 book_no;
+	u16 reg_offset;
+	u8 reg_val;
+};
+
+/*
+ *----------------------------------------------------------------------------
+ * @struct  aic3262_rate_divs |
+ *          Setting up the values to get different freqencies
+ *
+ * @field   u32 | mclk |
+ *          Master clock
+ * @field   u32 | rate |
+ *          sample rate
+ * @field   u8 | p_val |
+ *          value of p in PLL
+ * @field   u32 | pll_j |
+ *          value for pll_j
+ * @field   u32 | pll_d |
+ *          value for pll_d
+ * @field   u32 | dosr |
+ *          value to store dosr
+ * @field   u32 | ndac |
+ *          value for ndac
+ * @field   u32 | mdac |
+ *          value for mdac
+ * @field   u32 | aosr |
+ *          value for aosr
+ * @field   u32 | nadc |
+ *          value for nadc
+ * @field   u32 | madc |
+ *          value for madc
+ * @field   u32 | blck_N |
+ *          value for block N
+ */
+struct aic3262 {
+	struct mutex io_lock;
+	struct mutex irq_lock;
+	enum aic3262_type type;
+	struct device *dev;
+	int (*read_dev)(struct aic3262 *aic3262, unsigned int reg,
+			int bytes, void *dest);
+	int (*write_dev)(struct aic3262 *aic3262, unsigned int reg,
+			 int bytes, const void *src);
+
+	void *control_data;
+	unsigned int irq;
+	unsigned int irq_base;
+	u8 irq_masks_cur;
+	u8 irq_masks_cache;
+	/* Used over suspend/resume */
+	bool suspended;
+	u8 book_no;
+	u8 page_no;
+};
+
+struct aic3262_gpio_setup {
+	u8 used;		/* GPIO, GPI and GPO is used in the board, */
+				/* used = 1 else 0 */
+	u8 in;			/* GPIO is used as input, in = 1 else in = 0 */
+				/* GPI in = 1, GPO in = 0 */
+	unsigned int in_reg;	/* if GPIO is input,
+					register to write the mask. */
+	u8 in_reg_bitmask;	/* bitmask for 'value' to be
+					written into in_reg */
+	u8 in_reg_shift;	/* bits to shift to write 'value'
+					into in_reg */
+	u8 value;		/* value to be written
+					gpio_control_reg if GPIO */
+				/* is output, in_reg if its input */
+};
+
+struct aic3262_pdata {
+	unsigned int audio_mclk1;
+	unsigned int audio_mclk2;
+	unsigned int gpio_irq;	/* whether AIC3262 interrupts the host AP on */
+				/* a GPIO pin of AP */
+	unsigned int gpio_reset;/* is the codec being reset by a gpio*/
+				/* [host] pin, if yes provide the number. */
+	struct aic3262_gpio_setup *gpio;/* all gpio configuration */
+	int naudint_irq;	/* audio interrupt */
+	unsigned int irq_base;
+};
+
+static inline int aic3262_request_irq(struct aic3262 *aic3262, int irq,
+				      irq_handler_t handler,
+				      unsigned long irqflags, const char *name,
+				      void *data)
+{
+	if (!aic3262->irq_base)
+		return -EINVAL;
+
+	return request_threaded_irq(aic3262->irq_base + irq, NULL, handler,
+				    irqflags, name, data);
+}
+
+static inline int aic3262_free_irq(struct aic3262 *aic3262, int irq, void *data)
+{
+	if (!aic3262->irq_base)
+		return -EINVAL;
+
+	free_irq(aic3262->irq_base + irq, data);
+	return 0;
+}
+
+/* Device I/O API */
+int aic3262_reg_read(struct aic3262 *aic3262, unsigned int reg);
+int aic3262_reg_write(struct aic3262 *aic3262, unsigned int reg,
+		      unsigned char val);
+int aic3262_set_bits(struct aic3262 *aic3262, unsigned int reg,
+		     unsigned char mask, unsigned char val);
+int aic3262_bulk_read(struct aic3262 *aic3262, unsigned int reg,
+		      int count, u8 *buf);
+int aic3262_bulk_write(struct aic3262 *aic3262, unsigned int reg,
+		       int count, const u8 *buf);
+int aic3262_wait_bits(struct aic3262 *aic3262, unsigned int reg,
+		      unsigned char mask, unsigned char val, int delay,
+		      int counter);
+
+int aic3262_irq_init(struct aic3262 *aic3262);
+void aic3262_irq_exit(struct aic3262 *aic3262);
+
+#endif /* End of __MFD_AIC3262_CORE_H__ */
diff --git a/include/linux/mfd/tlv320aic3262-registers.h b/include/linux/mfd/tlv320aic3262-registers.h
new file mode 100644
index 000000000000..bdd7dfed80cd
--- /dev/null
+++ b/include/linux/mfd/tlv320aic3262-registers.h
@@ -0,0 +1,323 @@
+
+#ifndef __MFD_AIC3262_REGISTERS_H__
+#define __MFD_AIC3262_REGISTERS_H__
+
+#define MAKE_REG(book, page, offset) \
+	(unsigned int)((book << 16)|(page << 8)|offset)
+
+/* ****************** Book 0 Registers **************************************/
+
+/* ****************** Page 0 Registers **************************************/
+#define AIC3262_PAGE_SEL_REG		MAKE_REG(0, 0, 0)
+#define AIC3262_RESET_REG		MAKE_REG(0, 0, 1)
+#define AIC3262_REV_PG_ID		MAKE_REG(0, 0, 2)
+#define AIC3262_REV_MASK		(0b01110000)
+#define AIC3262_REV_SHIFT		4
+#define AIC3262_PG_MASK			(0b00000111)
+#define AIC3262_PG_SHIFT		0
+#define AIC3262_DAC_ADC_CLKIN_REG	MAKE_REG(0, 0, 4)
+#define AIC3262_PLL_CLKIN_REG		MAKE_REG(0, 0, 5)
+#define AIC3262_PLL_CLKIN_MASK		(0b00111100)
+#define AIC3262_PLL_CLKIN_SHIFT		2
+#define AIC3262_PLL_CLKIN_MCLK1		0
+#define AIC3262_PLL_CLKIN_BCLK1		1
+#define AIC3262_PLL_CLKIN_GPIO1		2
+#define AIC3262_PLL_CLKIN_DIN1		3
+#define AIC3262_PLL_CLKIN_BCLK2		4
+#define AIC3262_PLL_CLKIN_GPI1		5
+#define AIC3262_PLL_CLKIN_HF_REF_CLK	6
+#define AIC3262_PLL_CLKIN_GPIO2		7
+#define AIC3262_PLL_CLKIN_GPI2		8
+#define AIC3262_PLL_CLKIN_MCLK2		9
+#define AIC3262_CLK_VAL_MASK		0x7f
+#define AIC3262_PLL_CLK_RANGE_REG	MAKE_REG(0, 0, 5)
+#define AIC3262_PLL_PR_POW_REG		MAKE_REG(0, 0, 6)
+#define AIC3262_PLL_PVAL_MASK		0x70
+#define AIC3262_PLL_RVAL_MASK		0x0F
+
+#define AIC3262_ENABLE_CLK_MASK		0x80
+#define AIC3262_ENABLE_CLK		0x80
+
+#define AIC3262_PLL_J_REG		MAKE_REG(0, 0, 7)
+#define AIC3262_JVAL_MASK		0x3f
+#define AIC3262_PLL_D_MSB		MAKE_REG(0, 0, 8)
+#define AIC3262_DVAL_MSB_MASK		0xf
+#define AIC3262_DVAL_LSB_MASK		0xff
+#define AIC3262_PLL_D_LSB		MAKE_REG(0, 0, 9)
+#define AIC3262_PLL_CKIN_DIV		MAKE_REG(0, 0, 10)
+
+#define AIC3262_NDAC_DIV_POW_REG	MAKE_REG(0, 0, 11)
+#define AIC3262_MDAC_DIV_POW_REG	MAKE_REG(0, 0, 12)
+#define AIC3262_DOSR_MSB_REG		MAKE_REG(0, 0, 13)
+#define AIC3262_DOSR_MSB_MASK		0x3
+#define AIC3262_DOSR_LSB_REG		MAKE_REG(0, 0, 14)
+#define AIC3262_DOSR_LSB_MASK		0xFF
+
+#define AIC3262_NADC_DIV_POW_REG	MAKE_REG(0, 0, 18)
+#define AIC3262_MADC_DIV_POW_REG	MAKE_REG(0, 0, 19)
+#define AIC3262_AOSR_REG		MAKE_REG(0, 0, 20)
+#define AIC3262_CLKOUT_MUX		MAKE_REG(0, 0, 21)
+#define AIC3262_CLKOUT_MDIV_VAL		MAKE_REG(0, 0, 22)
+#define AIC3262_TIMER_REG		MAKE_REG(0, 0, 23)
+
+#define AIC3262_LF_CLK_CNTL		MAKE_REG(0, 0, 24)
+#define AIC3262_HF_CLK_CNTL_R1		MAKE_REG(0, 0, 25)
+#define AIC3262_HF_CLK_CNTL_R2		MAKE_REG(0, 0, 26)
+#define AIC3262_HF_CLK_CNTL_R3		MAKE_REG(0, 0, 27)
+#define AIC3262_HF_CLK_CNTL_R4		MAKE_REG(0, 0, 28)
+#define AIC3262_HF_CLK_TRIM_R1		MAKE_REG(0, 0, 29)
+#define AIC3262_HF_CLK_TRIM_R2		MAKE_REG(0, 0, 30)
+#define AIC3262_HF_CLK_TRIM_R3		MAKE_REG(0, 0, 31)
+#define AIC3262_HF_CLK_TRIM_R4		MAKE_REG(0, 0, 32)
+#define AIC3262_LDAC_POWER_MASK		0x80
+#define AIC3262_RDAC_POWER_MASK		0x08
+#define AIC3262_DAC_POWER_MASK		0x88
+#define AIC3262_DAC_FLAG		MAKE_REG(0, 0, 37)
+#define AIC3262_LADC_POWER_MASK		0x40
+#define AIC3262_RADC_POWER_MASK		0x04
+#define AIC3262_ADC_POWER_MASK		0x44
+#define AIC3262_ADC_FLAG                MAKE_REG(0, 0, 36)
+#define AIC3262_JACK_WITH_STEREO_HS	(0b00000010)
+#define AIC3262_JACK_WITH_MIC		(0b00110000)
+#define AIC3262_HEADSET_NOT_INSERTED	(0b00000011)
+
+#define AIC3262_INT_STICKY_FLAG1		MAKE_REG(0, 0, 42)
+#define AIC3262_LEFT_DAC_OVERFLOW_INT	0x80
+#define AIC3262_RIGHT_DAC_OVERFLOW_INT	0x40
+#define AIC3262_MINIDSP_D_BARREL_SHIFT_OVERFLOW_INT	0x20
+#define AIC3262_LEFT_ADC_OVERFLOW_INT	0x08
+#define AIC3262_RIGHT_ADC_OVERFLOW_INT	0x04
+#define AIC3262_MINIDSP_A_BARREL_SHIFT_OVERFLOW_INT	0x02
+#define AIC3262_INT_STICKY_FLAG2		MAKE_REG(0, 0, 44)
+#define AIC3262_LEFT_OUTPUT_DRIVER_OVERCURRENT_INT	0x80
+#define AIC3262_RIGHT_OUTPUT_DRIVER_OVERCURRENT_INT	0x40
+#define AIC3262_BUTTON_PRESS_INT			0x20
+#define AIC3262_HEADSET_PLUG_UNPLUG_INT			0x10
+#define AIC3262_LEFT_DRC_THRES_INT			0x08
+#define AIC3262_RIGHT_DRC_THRES_INT			0x04
+#define AIC3262_MINIDSP_D_STD_INT			0x02
+#define AIC3262_RIGHT_DRC_AUX_INT			0x01
+#define AIC3262_INT_STICKY_FLAG3		MAKE_REG(0, 0, 45)
+#define AIC3262_SPK_OVER_CURRENT_INT		0x80
+#define AIC3262_LEFT_AGC_NOISE_INT			0x40
+#define AIC3262_RIGHT_AGC_NOISE_INT			0x20
+#define AIC3262_INT1_CNTL		MAKE_REG(0, 0, 48)
+#define AIC3262_HEADSET_IN_MASK		0x80
+#define AIC3262_BUTTON_PRESS_MASK	0x40
+#define AIC3262_DAC_DRC_THRES_MASK	0x20
+#define AIC3262_AGC_NOISE_MASK		0x10
+#define AIC3262_OVER_CURRENT_MASK	0x08
+#define AIC3262_OVERFLOW_MASK		0x04
+#define AIC3262_SPK_OVERCURRENT_MASK	0x02
+#define AIC3262_INT2_CNTL		MAKE_REG(0, 0, 49)
+#define AIC3262_INT_FMT			MAKE_REG(0, 0, 51)
+
+#define AIC3262_DAC_PRB			MAKE_REG(0, 0, 60)
+#define AIC3262_ADC_PRB			MAKE_REG(0, 0, 61)
+#define AIC3262_PASI_DAC_DP_SETUP	MAKE_REG(0, 0, 63)
+
+#define AIC3262_DAC_MVOL_CONF		MAKE_REG(0, 0, 64)
+#define AIC3262_DAC_LR_MUTE_MASK	0xc
+#define AIC3262_DAC_LR_MUTE		0xc
+
+#define AIC3262_DAC_LVOL		MAKE_REG(0, 0, 65)
+#define AIC3262_DAC_RVOL		MAKE_REG(0, 0, 66)
+#define AIC3262_HP_DETECT		MAKE_REG(0, 0, 67)
+#define AIC3262_DRC_CNTL_R1		MAKE_REG(0, 0, 68)
+#define AIC3262_DRC_CNTL_R2		MAKE_REG(0, 0, 69)
+#define AIC3262_DRC_CNTL_R3		MAKE_REG(0, 0, 70)
+#define AIC3262_BEEP_CNTL_R1		MAKE_REG(0, 0, 71)
+#define AIC3262_BEEP_CNTL_R2		MAKE_REG(0, 0, 72)
+
+#define AIC3262_ADC_CHANNEL_POW		MAKE_REG(0, 0, 81)
+#define AIC3262_ADC_FINE_GAIN		MAKE_REG(0, 0, 82)
+#define AIC3262_LADC_VOL		MAKE_REG(0, 0, 83)
+#define AIC3262_RADC_VOL		MAKE_REG(0, 0, 84)
+#define AIC3262_ADC_PHASE		MAKE_REG(0, 0, 85)
+
+#define AIC3262_LAGC_CNTL		MAKE_REG(0, 0, 86)
+#define AIC3262_LAGC_CNTL_R2		MAKE_REG(0, 0, 87)
+#define AIC3262_LAGC_CNTL_R3		MAKE_REG(0, 0, 88)
+#define AIC3262_LAGC_CNTL_R4		MAKE_REG(0, 0, 89)
+#define AIC3262_LAGC_CNTL_R5		MAKE_REG(0, 0, 90)
+#define AIC3262_LAGC_CNTL_R6		MAKE_REG(0, 0, 91)
+#define AIC3262_LAGC_CNTL_R7		MAKE_REG(0, 0, 92)
+#define AIC3262_LAGC_CNTL_R8		MAKE_REG(0, 0, 93)
+
+#define AIC3262_RAGC_CNTL		MAKE_REG(0, 0, 94)
+#define AIC3262_RAGC_CNTL_R2		MAKE_REG(0, 0, 95)
+#define AIC3262_RAGC_CNTL_R3		MAKE_REG(0, 0, 96)
+#define AIC3262_RAGC_CNTL_R4		MAKE_REG(0, 0, 97)
+#define AIC3262_RAGC_CNTL_R5		MAKE_REG(0, 0, 98)
+#define AIC3262_RAGC_CNTL_R6		MAKE_REG(0, 0, 99)
+#define AIC3262_RAGC_CNTL_R7		MAKE_REG(0, 0, 100)
+#define AIC3262_RAGC_CNTL_R8		MAKE_REG(0, 0, 101)
+#define AIC3262_MINIDSP_ACCESS_CTRL	MAKE_REG(0, 0, 121)
+/* ****************** Page 1 Registers **************************************/
+#define AIC3262_PAGE_1			128
+
+#define AIC3262_POWER_CONF		MAKE_REG(0, 1, 1)
+
+#define AIC3262_AVDD_TO_DVDD_MASK	(0b00001000)
+#define	AIC3262_AVDD_TO_DVDD		0x8
+#define AIC3262_EXT_ANALOG_SUPPLY_MASK	(0b00000100)
+#define	AIC3262_EXT_ANALOG_SUPPLY_OFF	0x4
+
+#define AIC3262_LDAC_PTM		MAKE_REG(0, 1, 3)
+#define AIC3262_RDAC_PTM		MAKE_REG(0, 1, 4)
+#define AIC3262_CM_REG			MAKE_REG(0, 1, 8)
+#define AIC3262_HP_CTL			MAKE_REG(0, 1, 9)
+#define AIC3262_HP_DEPOP		MAKE_REG(0, 1, 11)
+#define AIC3262_RECV_DEPOP		MAKE_REG(0, 1, 12)
+#define AIC3262_MA_CNTL			MAKE_REG(0, 1, 17)
+#define AIC3262_LADC_PGA_MAL_VOL	MAKE_REG(0, 1, 18)
+#define AIC3262_RADC_PGA_MAR_VOL	MAKE_REG(0, 1, 19)
+
+#define AIC3262_LINE_AMP_CNTL_R1	MAKE_REG(0, 1, 22)
+#define AIC3262_LINE_AMP_CNTL_R2	MAKE_REG(0, 1, 23)
+
+#define AIC3262_HP_AMP_CNTL_R1		MAKE_REG(0, 1, 27)
+#define AIC3262_HP_AMP_CNTL_R2		MAKE_REG(0, 1, 28)
+#define AIC3262_HP_AMP_CNTL_R3		MAKE_REG(0, 1, 29)
+
+#define AIC3262_HPL_VOL			MAKE_REG(0, 1, 31)
+#define AIC3262_HPR_VOL			MAKE_REG(0, 1, 32)
+#define AIC3262_INT1_SEL_L		MAKE_REG(0, 1, 34)
+#define AIC3262_CHARGE_PUMP_CNTL	MAKE_REG(0, 1, 35)
+#define AIC3262_RAMP_CNTL_R1		MAKE_REG(0, 1, 36)
+#define AIC3262_RAMP_CNTL_R2		MAKE_REG(0, 1, 37)
+#define AIC3262_IN1L_SEL_RM		MAKE_REG(0, 1, 38)
+#define AIC3262_IN1R_SEL_RM		MAKE_REG(0, 1, 39)
+#define AIC3262_REC_AMP_CNTL_R5		MAKE_REG(0, 1, 40)
+#define AIC3262_RAMPR_VOL		MAKE_REG(0, 1, 41)
+#define AIC3262_RAMP_TIME_CNTL		MAKE_REG(0, 1, 42)
+#define AIC3262_SPK_AMP_CNTL_R1		MAKE_REG(0, 1, 45)
+#define AIC3262_SPK_AMP_CNTL_R2		MAKE_REG(0, 1, 46)
+#define AIC3262_SPK_AMP_CNTL_R3		MAKE_REG(0, 1, 47)
+#define AIC3262_SPK_AMP_CNTL_R4		MAKE_REG(0, 1, 48)
+#define AIC3262_MIC_BIAS_CNTL		MAKE_REG(0, 1, 51)
+
+#define AIC3262_LMIC_PGA_PIN		MAKE_REG(0, 1, 52)
+#define AIC3262_LMIC_PGA_PM_IN4		MAKE_REG(0, 1, 53)
+#define AIC3262_LMIC_PGA_MIN		MAKE_REG(0, 1, 54)
+#define AIC3262_RMIC_PGA_PIN		MAKE_REG(0, 1, 55)
+#define AIC3262_RMIC_PGA_PM_IN4		MAKE_REG(0, 1, 56)
+#define AIC3262_RMIC_PGA_MIN		MAKE_REG(0, 1, 57)
+#define AIC3262_HP_FLAG		        MAKE_REG(0, 1, 66)
+#define AIC3262_SPKL_POWER_MASK		0x2
+#define AIC3262_SPKR_POWER_MASK		0x1
+#define AIC3262_HPL_POWER_MASK		0x20
+#define AIC3262_HPR_POWER_MASK		0x10
+/* MIC PGA Gain Registers */
+#define AIC3262_MICL_PGA		MAKE_REG(0, 1, 59)
+#define AIC3262_MICR_PGA		MAKE_REG(0, 1, 60)
+#define AIC3262_HEADSET_TUNING1_REG	MAKE_REG(0, 1, 119)
+#define AIC3262_HEADSET_DETECTOR_PULSE_MASK (0b11000000)
+#define AIC3262_HEADSET_DETECTOR_PULSE_RESET (0b10000000)
+#define AIC3262_MIC_PWR_DLY		MAKE_REG(0, 1, 121)
+#define AIC3262_REF_PWR_DLY		MAKE_REG(0, 1, 122)
+#define AIC3262_CHIP_REF_PWR_ON_MASK	0x4
+#define AIC3262_CHIP_REF_PWR_ON		0x4
+/* ****************** Page 4 Registers **************************************/
+#define AIC3262_PAGE_4			512
+#define AIC3262_ASI1_BUS_FMT		MAKE_REG(0, 4, 1)
+#define AIC3262_ASI_SELECTION_MASK	(0b11100000)
+#define AIC3262_ASI_DATA_WORD_LENGTH_MASK	(0b00011000)
+#define AIC3262_ASI_BCLK_N_MASK		(0b01111111)
+#define AIC3262_ASI1_LCH_OFFSET		MAKE_REG(0, 4, 2)
+#define AIC3262_ASI1_RCH_OFFSET		MAKE_REG(0, 4, 3)
+#define AIC3262_ASI1_CHNL_SETUP		MAKE_REG(0, 4, 4)
+#define AIC3262_ASI1_MULTI_CH_SETUP_R1	MAKE_REG(0, 4, 5)
+#define AIC3262_ASI1_MULTI_CH_SETUP_R2	MAKE_REG(0, 4, 6)
+#define AIC3262_ASI1_ADC_INPUT_CNTL	MAKE_REG(0, 4, 7)
+#define AIC3262_ASI1_DAC_OUT_CNTL	MAKE_REG(0, 4, 8)
+#define AIC3262_ASI1_ADC_OUT_TRISTATE	MAKE_REG(0, 4, 9)
+#define AIC3262_ASI1_BWCLK_CNTL_REG	MAKE_REG(0, 4, 10)
+#define AIC3262_ASI1_BCLK_N_CNTL	MAKE_REG(0, 4, 11)
+#define AIC3262_ASI1_BCLK_N		MAKE_REG(0, 4, 12)
+#define AIC3262_ASI1_WCLK_N		MAKE_REG(0, 4, 13)
+#define AIC3262_ASI1_BWCLK_OUT_CNTL	MAKE_REG(0, 4, 14)
+#define AIC3262_ASI1_DOUT_CNTL		MAKE_REG(0, 4, 15)
+#define AIC3262_ASI2_BUS_FMT	        MAKE_REG(0, 4, 17)
+#define AIC3262_ASI2_LCH_OFFSET		MAKE_REG(0, 4, 18)
+#define AIC3262_ASI2_ADC_INPUT_CNTL	MAKE_REG(0, 4, 23)
+#define AIC3262_ASI2_DAC_OUT_CNTL	MAKE_REG(0, 4, 24)
+#define AIC3262_ASI2_BWCLK_CNTL_REG	MAKE_REG(0, 4, 26)
+#define AIC3262_ASI2_BCLK_N_CNTL	MAKE_REG(0, 4, 27)
+#define AIC3262_ASI2_BCLK_N		MAKE_REG(0, 4, 28)
+#define AIC3262_ASI2_WCLK_N		MAKE_REG(0, 4, 29)
+#define AIC3262_ASI2_BWCLK_OUT_CNTL	MAKE_REG(0, 4, 30)
+#define AIC3262_ASI2_DOUT_CNTL		MAKE_REG(0, 4, 31)
+#define AIC3262_ASI3_BUS_FMT		MAKE_REG(0, 4, 33)
+#define AIC3262_ASI3_LCH_OFFSET		MAKE_REG(0, 4, 34)
+#define AIC3262_ASI3_ADC_INPUT_CNTL	MAKE_REG(0, 4, 39)
+#define AIC3262_ASI3_DAC_OUT_CNTL	MAKE_REG(0, 4, 40)
+#define AIC3262_ASI3_BWCLK_CNTL_REG	MAKE_REG(0, 4, 42)
+#define AIC3262_ASI3_BCLK_N_CNTL	MAKE_REG(0, 4, 43)
+#define AIC3262_ASI3_BCLK_N		MAKE_REG(0, 4, 44)
+#define AIC3262_ASI3_WCLK_N		MAKE_REG(0, 4, 45)
+#define AIC3262_ASI3_BWCLK_OUT_CNTL	MAKE_REG(0, 4, 46)
+#define AIC3262_ASI3_DOUT_CNTL		MAKE_REG(0, 4, 47)
+#define AIC3262_GPIO1_IO_CNTL		MAKE_REG(0, 4, 86)
+#define AIC3262_GPIO_D6_D2		(0b01111100)
+#define AIC3262_GPIO_D2_SHIFT		(2)
+#define AIC3262_GPIO_D1_SHIFT		(1)
+#define AIC3262_GPIO_D4_SHIFT		(4)
+#define AIC3262_GPIO2_IO_CNTL		MAKE_REG(0, 4, 87)
+#define AIC3262_GPI1_EN			MAKE_REG(0, 4, 91)
+#define AIC3262_GPI1_D2_D1		(0b00000110)
+#define AIC3262_GPI2_D5_D4		(0b00110000)
+#define AIC3262_GPI2_EN			MAKE_REG(0, 4, 92)
+#define AIC3262_GPO1_OUT_CNTL		MAKE_REG(0, 4, 96)
+#define AIC3262_GPO1_D4_D1		(0b00011110)
+#define AIC3262_DMIC_INPUT_CNTL		MAKE_REG(0, 4, 101)
+#define AIC3262_DMIC_CONFIGURE_MASK	(0b00011111)
+#define AIC3262_DMIC_CONFIGURE_SHIFT	(0)
+#define AIC3262_DMIC_GPI1_LEFT_GPI1_RIGHT	(0)
+#define AIC3262_DMIC_GPI2_LEFT_GPI2_RIGHT	(1)
+#define AIC3262_DMIC_DIN1_LEFT_DIN1_RIGHT	(2)
+#define AIC3262_DMIC_DIN2_LEFT_DIN2_RIGHT	(3)
+#define AIC3262_DMIC_GPI01_LEFT_GPI01_RIGHT	(4)
+#define AIC3262_DMIC_GPI02_LEFT_GPI02_RIGHT	(5)
+#define AIC3262_DMIC_MCLK2_LEFT_MCLK2_RIGHT	(6)
+#define AIC3262_DMIC_GPI1_LEFT_GPI2_RIGHT	(7)
+#define AIC3262_DMIC_GPI1_LEFT_DIN1_RIGHT	(8)
+#define AIC3262_DMIC_GPI1_LEFT_DIN2_RIGHT	(9)
+#define AIC3262_DMIC_GPI1_LEFT_GPIO1_RIGHT	(10)
+#define AIC3262_DMIC_GPI1_LEFT_GPIO2_RIGHT	(11)
+#define AIC3262_DMIC_GPI1_LEFT_MCLK2_RIGHT	(12)
+#define AIC3262_DMIC_GPI2_LEFT_DIN1_RIGHT	(13)
+#define AIC3262_DMIC_GPI2_LEFT_DIN2_RIGHT	(14)
+#define AIC3262_DMIC_GPI2_LEFT_GPIO1_RIGHT	(15)
+#define AIC3262_DMIC_GPI2_LEFT_GPIO2_RIGHT	(16)
+#define AIC3262_DMIC_GPI2_LEFT_MCLK2_RIGHT	(17)
+#define AIC3262_DMIC_DIN1_LEFT_DIN2_RIGHT	(18)
+#define AIC3262_DMIC_DIN1_LEFT_GPIO1_RIGHT	(19)
+#define AIC3262_DMIC_DIN1_LEFT_GPIO2_RIGHT	(20)
+#define AIC3262_DMIC_DIN1_LEFT_MCLK2_RIGHT	(21)
+#define AIC3262_DMIC_DIN2_LEFT_GPIO1_RIGHT	(22)
+#define AIC3262_DMIC_DIN2_LEFT_GPIO2_RIGHT	(23)
+#define AIC3262_DMIC_DIN2_LEFT_MCLK2_RIGHT	(24)
+#define AIC3262_DMIC_GPI01_LEFT_GPI02_RIGHT	(25)
+#define AIC3262_DMIC_GPI01_LEFT_MCLK2_RIGHT	(26)
+#define AIC3262_DMIC_GPI02_LEFT_MCLK2_RIGHT	(27)
+#define AIC3262_MINIDSP_DATA_PORT_CNTL	MAKE_REG(0, 4, 118)
+
+#define AIC3262_DAC_ASI_LR_UNMUTE_MASK	0x50
+#define AIC3262_DAC_ASI_LR_UNMUTE	0x50
+#define AIC3262_WCLK_BCLK_MASTER_MASK (0b00100110)
+#define AIC3262_WCLK_MASTER_MASK (0b00100000)
+#define AIC3262_BCLK_MASTER_MASK (0b00000100)
+#define AIC3262_BCLK_OFFSET_MASK (0b11111111)
+#define AIC3262_ASI_INTERFACE_MASK (0b11100000)
+#define AIC3262_WCLK_OUT_MASK (0b00100000)
+#define AIC3262_BCLK_OUT_MASK (0b00000100)
+#define AIC3262_BCLK_INV_MASK (0b00000010)
+
+#define AIC3262_ADC_ADAPTIVE_CRAM_REG    MAKE_REG(40, 0, 1)
+#define AIC3262_DAC_ADAPTIVE_BANK1_REG   MAKE_REG(80, 0, 1)
+#define AIC3262_DAC_ADAPTIVE_BANK2_REG   MAKE_REG(82, 0, 1)
+#define AIC3262_ADC_DATAPATH_SETUP      MAKE_REG(0, 0, 81)
+#define AIC3262_DAC_DATAPATH_SETUP      MAKE_REG(0, 0, 63)
+
+#endif
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 511ced59ef1a..7ae86b956710 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -1,5 +1,4 @@
 /*
- * include/linux/mfd/tps65090.h
  * Core driver interface for TI TPS65090 PMIC family
  *
  * Copyright (C) 2012 NVIDIA Corporation
@@ -23,31 +22,60 @@
 #ifndef __LINUX_MFD_TPS65090_H
 #define __LINUX_MFD_TPS65090_H
 
-#include <linux/rtc.h>
+#include <linux/irq.h>
+#include <linux/regmap.h>
 
-struct tps65090_subdev_info {
-	int		id;
-	const char	*name;
-	void		*platform_data;
+struct tps65090 {
+	struct device		*dev;
+	struct regmap		*rmap;
+	struct irq_chip		irq_chip;
+	struct mutex		irq_lock;
+	int			irq_base;
 };
 
 struct tps65090_platform_data {
 	int irq_base;
-	int num_subdevs;
-	struct tps65090_subdev_info *subdevs;
+	struct tps65090_regulator_platform_data **reg_pdata;
+	int num_reg_pdata;
 };
 
 /*
  * NOTE: the functions below are not intended for use outside
  * of the TPS65090 sub-device drivers
  */
-extern int tps65090_write(struct device *dev, int reg, uint8_t val);
-extern int tps65090_writes(struct device *dev, int reg, int len, uint8_t *val);
-extern int tps65090_read(struct device *dev, int reg, uint8_t *val);
-extern int tps65090_reads(struct device *dev, int reg, int len, uint8_t *val);
-extern int tps65090_set_bits(struct device *dev, int reg, uint8_t bit_num);
-extern int tps65090_clr_bits(struct device *dev, int reg, uint8_t bit_num);
-extern int tps65090_update(struct device *dev, int reg, uint8_t val,
-			   uint8_t bit_num);
+static inline int tps65090_write(struct device *dev, int reg, uint8_t val)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+
+	return regmap_write(tps->rmap, reg, val);
+}
+
+static inline int tps65090_read(struct device *dev, int reg, uint8_t *val)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+	unsigned int temp_val;
+	int ret;
+
+	ret = regmap_read(tps->rmap, reg, &temp_val);
+	if (!ret)
+		*val = temp_val;
+	return ret;
+}
+
+static inline int tps65090_set_bits(struct device *dev, int reg,
+		uint8_t bit_num)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+
+	return regmap_update_bits(tps->rmap, reg, BIT(bit_num), ~0u);
+}
+
+static inline int tps65090_clr_bits(struct device *dev, int reg,
+		uint8_t bit_num)
+{
+	struct tps65090 *tps = dev_get_drvdata(dev);
+
+	return regmap_update_bits(tps->rmap, reg, BIT(bit_num), 0u);
+}
 
 #endif /*__LINUX_MFD_TPS65090_H */
diff --git a/include/linux/mfd/tps80031.h b/include/linux/mfd/tps80031.h
index b3b9480ce596..2fa29e910ba2 100644
--- a/include/linux/mfd/tps80031.h
+++ b/include/linux/mfd/tps80031.h
@@ -184,9 +184,12 @@ struct tps80031_pupd_init_data {
 	int setting;
 };
 
+struct tps80031_bg_platform_data {
+	int irq_base;
+	int battery_present;
+};
+
 struct tps80031_platform_data {
-	int num_subdevs;
-	struct tps80031_subdev_info *subdevs;
 	int gpio_base;
 	int irq_base;
 	struct tps80031_32kclock_plat_data *clk32k_pdata;
@@ -197,12 +200,13 @@ struct tps80031_platform_data {
 	bool use_power_off;
 	struct tps80031_pupd_init_data *pupd_init_data;
 	int pupd_init_data_size;
+	struct tps80031_regulator_platform_data **regulator_pdata;
+	int num_regulator_pdata;
+	struct tps80031_rtc_platform_data *rtc_pdata;
+	struct tps80031_bg_platform_data *bg_pdata;
+	struct tps80031_charger_platform_data *battery_charger_pdata;
 };
 
-struct tps80031_bg_platform_data {
-	int irq_base;
-	int battery_present;
-};
 
 /*
  * NOTE: the functions below are not intended for use outside
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index 8f17619931ab..4d50754f339e 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -188,7 +188,11 @@ struct mmc_card {
 #define MMC_STATE_ULTRAHIGHSPEED (1<<5)		/* card is in ultra high speed mode */
 #define MMC_STATE_DOING_BKOPS	(1<<6)		/* Card doing bkops */
 #define MMC_STATE_NEED_BKOPS	(1<<7)		/* Card needs to do bkops */
-#define MMC_CARD_SDXC		(1<<6)		/* card is SDXC */
+#define MMC_CARD_SDXC		(1<<8)		/* card is SDXC */
+#define MMC_CARD_REMOVED	(1<<9)		/* card has been removed */
+#define MMC_STATE_HIGHSPEED_200	(1<<10)		/* card is in HS200 mode */
+#define MMC_STATE_SLEEP		(1<<11)		/* card is in sleep state */
+
 	unsigned int		quirks; 	/* card quirks */
 #define MMC_QUIRK_LENIENT_FN0	(1<<0)		/* allow SDIO FN0 writes outside of the VS CCCR range */
 #define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1)	/* use func->cur_blksize */
@@ -332,6 +336,9 @@ static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data)
 #define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
 #define mmc_card_doing_bkops(c) ((c)->state & MMC_STATE_DOING_BKOPS)
 #define mmc_card_need_bkops(c) ((c)->state & MMC_STATE_NEED_BKOPS)
+#define mmc_card_removed(c)	((c) && ((c)->state & MMC_CARD_REMOVED))
+#define mmc_card_is_sleep(c)	((c)->state & MMC_STATE_SLEEP)
+
 #define mmc_card_set_present(c)	((c)->state |= MMC_STATE_PRESENT)
 #define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
 #define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED)
@@ -339,7 +346,10 @@ static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data)
 #define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR)
 #define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
 #define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
+#define mmc_card_set_removed(c) ((c)->state |= MMC_CARD_REMOVED)
+#define mmc_card_set_sleep(c)	((c)->state |= MMC_STATE_SLEEP)
 
+#define mmc_card_clr_sleep(c)	((c)->state &= ~MMC_STATE_SLEEP)
 /*
  * Quirk add/remove for MMC products.
  */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 8c0bf3f2a36f..0441661ad59a 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -232,6 +232,13 @@ struct mmc_host {
 #define MMC_CAP_CMD23		(1 << 30)	/* CMD23 supported. */
 #define MMC_CAP_BKOPS		(1 << 31)	/* Host supports BKOPS */
 
+	unsigned int		caps2;			/* More host capabilities */
+#define MMC_CAP2_BOOTPART_NOACC	(1 << 0)	/* Boot partition no access */
+#define MMC_CAP2_CACHE_CTRL		(1 << 1)	/* Allow cache control */
+#define MMC_CAP2_POWEROFF_NOTIFY	(1 << 2)	/* Notify poweroff supported */
+#define MMC_CAP2_NO_MULTI_READ	(1 << 3)	/* Multiblock reads don't work */
+#define MMC_CAP2_NO_SLEEP_CMD		(1 << 4)	/* Don't allow sleep command */
+
 	mmc_pm_flag_t		pm_caps;	/* supported pm features */
 
 #ifdef CONFIG_MMC_CLKGATE
@@ -401,6 +408,9 @@ int mmc_host_enable(struct mmc_host *host);
 int mmc_host_disable(struct mmc_host *host);
 int mmc_host_lazy_disable(struct mmc_host *host);
 int mmc_pm_notify(struct notifier_block *notify_block, unsigned long, void *);
+int mmc_speed_class_control(struct mmc_host *host,
+	unsigned int speed_class_ctrl_arg);
+
 
 static inline void mmc_set_disable_delay(struct mmc_host *host,
 					 unsigned int disable_delay)
diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h
index 1ebcf9ba1256..e65bf7c9dab0 100644
--- a/include/linux/mmc/sd.h
+++ b/include/linux/mmc/sd.h
@@ -19,6 +19,10 @@
 #define SD_SEND_IF_COND           8   /* bcr  [11:0] See below   R7  */
 #define SD_SWITCH_VOLTAGE         11  /* ac                      R1  */
 
+  /* class 2 */
+#define SD_SEND_TUNING_PATTERN   19   /* adtc                    R1  */
+#define SD_SPEED_CLASS_CONTROL   20   /* ac                      R1b */
+
   /* class 10 */
 #define SD_SWITCH                 6   /* adtc [31:0] See below   R1  */
 
@@ -91,4 +95,13 @@
 #define SD_SWITCH_ACCESS_DEF	0
 #define SD_SWITCH_ACCESS_HS	1
 
+/*
+ * SD_SPEED_CLASS_CONTROL definitions
+ */
+#define SD_SPEED_CLASS_CONTROL_START_REC		0x0
+#define SD_SPEED_CLASS_CONTROL_CREATE_DIR		0x1
+#define SD_SPEED_CLASS_CONTROL_UPDATE_CI		0x4
+
+
 #endif /* LINUX_MMC_SD_H */
+
diff --git a/include/linux/nvhost.h b/include/linux/nvhost.h
index cde63fa6abb7..d7d8ad04653d 100644
--- a/include/linux/nvhost.h
+++ b/include/linux/nvhost.h
@@ -172,6 +172,10 @@ struct nvhost_driver {
 	/* Allocates a context handler for the device */
 	struct nvhost_hwctx_handler *(*alloc_hwctx_handler)(u32 syncpt,
 			u32 waitbase, struct nvhost_channel *ch);
+
+	/* Clock gating callbacks */
+	int (*prepare_clockoff)(struct nvhost_device *dev);
+	void (*finalize_clockon)(struct nvhost_device *dev);
 };
 
 extern int nvhost_driver_register(struct nvhost_driver *);
@@ -209,4 +213,6 @@ u32 nvhost_syncpt_read_ext(struct nvhost_device *dev, u32 id);
 int nvhost_syncpt_wait_timeout_ext(struct nvhost_device *dev, u32 id, u32 thresh,
 	u32 timeout, u32 *value);
 
+void nvhost_scale3d_set_throughput_hint(int hint);
+
 #endif
diff --git a/include/linux/nvmap.h b/include/linux/nvmap.h
index 553a7bd01a6d..692956b2fc4f 100644
--- a/include/linux/nvmap.h
+++ b/include/linux/nvmap.h
@@ -3,7 +3,7 @@
  *
  * structure declarations for nvmem and nvmap user-space ioctls
  *
- * Copyright (c) 2009-2012, NVIDIA Corporation.
+ * Copyright (c) 2009-2012, NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -49,6 +49,7 @@
 #define NVMAP_HANDLE_CACHE_FLAG      (0x3ul << 0)
 
 #define NVMAP_HANDLE_SECURE          (0x1ul << 2)
+#define NVMAP_HANDLE_ZEROED_PAGES    (0x1ul << 3)
 
 #if defined(__KERNEL__)
 
diff --git a/include/linux/platform_data/tegra_nor.h b/include/linux/platform_data/tegra_nor.h
index cd8faff2f1cd..4bd980d2195b 100644
--- a/include/linux/platform_data/tegra_nor.h
+++ b/include/linux/platform_data/tegra_nor.h
@@ -1,10 +1,5 @@
 /*
- * include/linux/platform_data/tegra_nor.h
- *
- * Copyright (C) 2010 - 2011 NVIDIA Corporation.
- *
- * Author:
- *	Raghavendra V K <rvk@nvidia.com>
+ * Copyright (C) 2010-2012, NVIDIA Corporation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -15,6 +10,11 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
+ * include/linux/platform_data/tegra_nor.h
+ *
+ * Author:
+ *	Raghavendra V K <rvk@nvidia.com>
+ *
  */
 
 #ifndef __MACH_TEGRA_NOR_PDATA_H
@@ -22,11 +22,45 @@
 
 #include <asm/mach/flash.h>
 
+typedef enum {
+	NorMuxMode_ADNonMux,
+	NorMuxMode_ADMux,
+}NorMuxMode;
+
+typedef enum {
+	NorPageLength_Unsupported,
+	NorPageLength_4Word,
+	NorPageLength_8Word,
+}NorPageLength;
+
+typedef enum {
+	NorBurstLength_CntBurst,
+	NorBurstLength_8Word,
+	NorBurstLength_16Word,
+	NorBurstLength_32Word,
+}NorBurstLength;
+
+typedef enum {
+	NorReadMode_Async,
+	NorReadMode_Page,
+	NorReadMode_Burst,
+}NorReadMode;
+
+typedef enum {
+	NorReadyActive_WithData,
+	NorReadyActive_BeforeData,
+}NorReadyActive;
+
 struct tegra_nor_chip_parms {
 	struct {
 		uint32_t timing0;
 		uint32_t timing1;
 	} timing_default, timing_read;
+	NorMuxMode MuxMode;
+	NorReadMode ReadMode;
+	NorPageLength PageLength;
+	NorBurstLength BurstLength;
+	NorReadyActive ReadyActive;
 };
 
 struct tegra_nor_platform_data {
diff --git a/include/linux/platform_data/tegra_usb.h b/include/linux/platform_data/tegra_usb.h
index 6499eeaff6a3..9ad666f987ea 100644
--- a/include/linux/platform_data/tegra_usb.h
+++ b/include/linux/platform_data/tegra_usb.h
@@ -65,17 +65,6 @@ struct tegra_ulpi_config {
 };
 
 /**
- * configuration structure for setting up hsic phy
- */
-struct tegra_hsic_config {
-	u8 sync_start_delay;
-	u8 idle_wait_delay;
-	u8 term_range_adj;
-	u8 elastic_underrun_limit;
-	u8 elastic_overrun_limit;
-};
-
-/**
  * Platform specific operations that will be controlled
  * during the phy operations.
  */
@@ -134,7 +123,6 @@ struct tegra_usb_platform_data {
 	union {
 		struct tegra_utmi_config utmi;
 		struct tegra_ulpi_config ulpi;
-		struct tegra_hsic_config hsic;
 	} u_cfg;
 
 	struct tegra_usb_phy_platform_ops *ops;
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 1a80bc77517d..65ca5ff023ea 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -153,6 +153,7 @@ enum regulator_type {
  * this type.
  *
  * @name: Identifying name for the regulator.
+ * @supply_name: Identifying the regulator supply
  * @id: Numerical identifier for the regulator.
  * @n_voltages: Number of selectors available for ops.list_voltage().
  * @ops: Regulator operations table.
@@ -162,6 +163,7 @@ enum regulator_type {
  */
 struct regulator_desc {
 	const char *name;
+	const char *supply_name;
 	int id;
 	unsigned n_voltages;
 	struct regulator_ops *ops;
diff --git a/include/linux/regulator/tps51632-regulator.h b/include/linux/regulator/tps51632-regulator.h
new file mode 100644
index 000000000000..6dd0b9239698
--- /dev/null
+++ b/include/linux/regulator/tps51632-regulator.h
@@ -0,0 +1,54 @@
+/*
+ * tps51632-regulator.h -- TPS51632 regulator
+ *
+ * Interface for regulator driver for TPS51632 3-2-1 Phase D-Cap Step Down
+ * Driverless Controller with serial VID control and DVFS.
+ *
+ * Copyright (C) 2012 NVIDIA Corporation
+
+ * Author: Laxman Dewangan <ldewangan@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA	02110-1301, USA.
+ *
+ */
+
+#ifndef __LINUX_REGULATOR_TPS51632_H
+#define __LINUX_REGULATOR_TPS51632_H
+
+/*
+ * struct tps51632_regulator_platform_data - tps51632 regulator platform data.
+ *
+ * @reg_init_data: The regulator init data.
+ * @enable_pwm: Enable PWM DVFS or not.
+ * @dvfs_step_20mV: Step for DVFS is 20mV or 10mV.
+ * @enable_vmax_alarm: Enable maximum voltage alarm or not.
+ * @enable_overcurrent_alram: Enable overcurrent alarm or not.
+ * @max_voltage_uV: Maximum possible voltage for alarm.
+ * @base_voltage_uV: Base voltage when PWM enabled.
+ * slew_rate_uv_per_us: Slew rate uV/us. The values can be
+ *		6000 to 48000uV/us.
+ */
+struct tps51632_regulator_platform_data {
+	struct regulator_init_data *reg_init_data;
+	bool enable_pwm;
+	bool dvfs_step_20mV;
+	bool enable_vmax_alarm;
+	bool enable_overcurrent_alram;
+	int max_voltage_uV;
+	int base_voltage_uV;
+	unsigned int slew_rate_uv_per_us;
+};
+
+#endif /* __LINUX_REGULATOR_TPS51632_H */
diff --git a/include/linux/regulator/tps65090-regulator.h b/include/linux/regulator/tps65090-regulator.h
index 341d53ec994a..785ca84efa8b 100644
--- a/include/linux/regulator/tps65090-regulator.h
+++ b/include/linux/regulator/tps65090-regulator.h
@@ -1,24 +1,19 @@
 /*
- * include/linux/regulator/tps65090-regulator.h
+ * Regulator driver interface for TI TPS65090 PMIC family
  *
- * Interface for regulator driver for TI TPS65090 PMIC family
- *
- * Copyright (C) 2012 NVIDIA Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
+
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+
+ * This program is distributed in the hope it will be useful, but WITHOUT
  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to  Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- *
+
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  */
 
 #ifndef __REGULATOR_TPS65090_H
@@ -29,32 +24,36 @@
 #define tps65090_rails(_name) "tps65090_"#_name
 
 enum {
-	TPS65090_ID_DCDC1,
-	TPS65090_ID_DCDC2,
-	TPS65090_ID_DCDC3,
-	TPS65090_ID_FET1,
-	TPS65090_ID_FET2,
-	TPS65090_ID_FET3,
-	TPS65090_ID_FET4,
-	TPS65090_ID_FET5,
-	TPS65090_ID_FET6,
-	TPS65090_ID_FET7,
+	TPS65090_REGULATOR_DCDC1,
+	TPS65090_REGULATOR_DCDC2,
+	TPS65090_REGULATOR_DCDC3,
+	TPS65090_REGULATOR_LDO1,
+	TPS65090_REGULATOR_LDO2,
+	TPS65090_REGULATOR_FET1,
+	TPS65090_REGULATOR_FET2,
+	TPS65090_REGULATOR_FET3,
+	TPS65090_REGULATOR_FET4,
+	TPS65090_REGULATOR_FET5,
+	TPS65090_REGULATOR_FET6,
+	TPS65090_REGULATOR_FET7,
 };
 
 /*
  * struct tps65090_regulator_platform_data
  *
- * @regulator: The regulator init data.
- * @init_uV: initial micro volts which need to be set.
- * @init_enable: Enable or do not enable the rails during initialization.
- * @init_apply: Init parameter applied or not.
- * @slew_rate_uV_per_us: Slew rate microvolt per microsec.
+ * @reg_init_data: The regulator init data.
+ * @id: Regulator ID.
+ * @enable_ext_control: Enable extrenal control or not. Only available for
+ *	DCDC1, DCDC2 and DCDC3.
+ * @gpio: Gpio number if external control is enabled and controlled through
+ *	gpio.
  */
 
 struct tps65090_regulator_platform_data {
-	struct regulator_init_data regulator;
-	int slew_rate_uV_per_us;
-	unsigned int flags;
+	int id;
+	bool enable_ext_control;
+	int gpio;
+	struct regulator_init_data *reg_init_data;
 };
 
 #endif	/* __REGULATOR_TPS65090_H */
diff --git a/include/linux/regulator/tps80031-regulator.h b/include/linux/regulator/tps80031-regulator.h
index 4dfdf7950918..f51fd24feff8 100644
--- a/include/linux/regulator/tps80031-regulator.h
+++ b/include/linux/regulator/tps80031-regulator.h
@@ -29,23 +29,26 @@
 #define tps80031_rails(_name) "tps80031_"#_name
 
 enum {
-	TPS80031_ID_VIO,
-	TPS80031_ID_SMPS1,
-	TPS80031_ID_SMPS2,
-	TPS80031_ID_SMPS3,
-	TPS80031_ID_SMPS4,
-	TPS80031_ID_VANA,
-	TPS80031_ID_LDO1,
-	TPS80031_ID_LDO2,
-	TPS80031_ID_LDO3,
-	TPS80031_ID_LDO4,
-	TPS80031_ID_LDO5,
-	TPS80031_ID_LDO6,
-	TPS80031_ID_LDO7,
-	TPS80031_ID_LDOLN,
-	TPS80031_ID_LDOUSB,
-	TPS80031_ID_VBUS,
-	TPS80031_ID_CHARGER,
+	TPS80031_REGULATOR_VIO,
+	TPS80031_REGULATOR_SMPS1,
+	TPS80031_REGULATOR_SMPS2,
+	TPS80031_REGULATOR_SMPS3,
+	TPS80031_REGULATOR_SMPS4,
+	TPS80031_REGULATOR_VANA,
+	TPS80031_REGULATOR_LDO1,
+	TPS80031_REGULATOR_LDO2,
+	TPS80031_REGULATOR_LDO3,
+	TPS80031_REGULATOR_LDO4,
+	TPS80031_REGULATOR_LDO5,
+	TPS80031_REGULATOR_LDO6,
+	TPS80031_REGULATOR_LDO7,
+	TPS80031_REGULATOR_LDOLN,
+	TPS80031_REGULATOR_LDOUSB,
+	TPS80031_REGULATOR_VBUS,
+	TPS80031_REGULATOR_REGEN1,
+	TPS80031_REGULATOR_REGEN2,
+	TPS80031_REGULATOR_SYSEN,
+	TPS80031_REGULATOR_CHARGER,
 };
 
 
@@ -66,7 +69,8 @@ enum {
 /*
  * struct tps80031_regulator_platform_data - tps80031 regulator platform data.
  *
- * @regulator: The regulator init data.
+ * @regulator_id" Regulator ID.
+ * @reg_init_data: The regulator init data.
  * @init_uV: initial micro volts which need to be set.
  * @init_enable: Enable or do not enable the rails during initialization.
  * @init_apply: Init parameter applied or not.
@@ -80,7 +84,8 @@ enum {
  */
 
 struct tps80031_regulator_platform_data {
-	struct regulator_init_data regulator;
+	int regulator_id;
+	struct regulator_init_data *reg_init_data;
 	int init_uV;
 	unsigned init_enable:1;
 	unsigned init_apply:1;
diff --git a/include/linux/tegra_nvavp.h b/include/linux/tegra_nvavp.h
index 6774d0eaa7ef..250eee379de9 100644
--- a/include/linux/tegra_nvavp.h
+++ b/include/linux/tegra_nvavp.h
@@ -1,7 +1,7 @@
 /*
  * include/linux/tegra_nvavp.h
  *
- * Copyright (C) 2011 NVIDIA Corp.
+ * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
  *
  * This file is licensed under the terms of the GNU General Public License
  * version 2. This program is licensed "as is" without any warranty of any
@@ -89,8 +89,12 @@ struct nvavp_clock_stay_on_state_args {
 					__u32)
 #define NVAVP_IOCTL_FORCE_CLOCK_STAY_ON	_IOW(NVAVP_IOCTL_MAGIC, 0x67, \
 					struct nvavp_clock_stay_on_state_args)
+#define NVAVP_IOCTL_ENABLE_AUDIO_CLOCKS	 _IOWR(NVAVP_IOCTL_MAGIC, 0x68, \
+					struct nvavp_clock_args)
+#define NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS _IOWR(NVAVP_IOCTL_MAGIC, 0x69, \
+					struct nvavp_clock_args)
 
 #define NVAVP_IOCTL_MIN_NR		_IOC_NR(NVAVP_IOCTL_SET_NVMAP_FD)
-#define NVAVP_IOCTL_MAX_NR		_IOC_NR(NVAVP_IOCTL_FORCE_CLOCK_STAY_ON)
+#define NVAVP_IOCTL_MAX_NR		_IOC_NR(NVAVP_IOCTL_DISABLE_AUDIO_CLOCKS)
 
 #endif /* __LINUX_TEGRA_NVAVP_H */
diff --git a/include/linux/tegra_uart.h b/include/linux/tegra_uart.h
index 38912ea97068..f51b373f8025 100644
--- a/include/linux/tegra_uart.h
+++ b/include/linux/tegra_uart.h
@@ -1,6 +1,6 @@
 /* include/linux/tegra_uart.h
  *
- * Copyright (C) 2011 NVIDIA Corporation
+ * Copyright (C) 2011-2012 NVIDIA Corporation
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -33,6 +33,12 @@ struct tegra_uart_platform_data {
 	struct uart_clk_parent *parent_clk_list;
 	int parent_clk_count;
 	bool is_loopback;
+	bool is_irda;
+	int (*irda_init)(void);
+	int (*irda_mode_switch)(int);
+	void (*irda_start)(void);
+	void (*irda_shutdown)(void);
+	void (*irda_remove)(void);
 };
 
 int tegra_uart_is_tx_empty(struct uart_port *);
diff --git a/include/linux/throughput_ioctl.h b/include/linux/throughput_ioctl.h
new file mode 100644
index 000000000000..96e57399b2e9
--- /dev/null
+++ b/include/linux/throughput_ioctl.h
@@ -0,0 +1,39 @@
+/*
+ * include/linux/throughput_ioctl.h
+ *
+ * ioctl declarations for throughput miscdev
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __TEGRA_THROUGHPUT_IOCTL_H
+#define __TEGRA_THROUGHPUT_IOCTL_H
+
+#include <linux/ioctl.h>
+
+#define TEGRA_THROUGHPUT_MAGIC 'g'
+
+struct tegra_throughput_target_fps_args {
+	__u32 target_fps;
+};
+
+#define TEGRA_THROUGHPUT_IOCTL_TARGET_FPS \
+	_IOW(TEGRA_THROUGHPUT_MAGIC, 1, struct tegra_throughput_target_fps_args)
+#define TEGRA_THROUGHPUT_IOCTL_MAXNR \
+	(_IOC_NR(TEGRA_THROUGHPUT_IOCTL_TARGET_FPS))
+
+#endif /* !defined(__TEGRA_THROUGHPUT_IOCTL_H) */
+
diff --git a/include/linux/usb/f_accessory.h b/include/linux/usb/f_accessory.h
index 5b2dcf9728e1..61ebe0aabc5b 100644
--- a/include/linux/usb/f_accessory.h
+++ b/include/linux/usb/f_accessory.h
@@ -36,13 +36,15 @@
 #define ACCESSORY_STRING_URI            4
 #define ACCESSORY_STRING_SERIAL         5
 
-/* Control request for retrieving device's protocol version (currently 1)
+/* Control request for retrieving device's protocol version
  *
  *	requestType:    USB_DIR_IN | USB_TYPE_VENDOR
  *	request:        ACCESSORY_GET_PROTOCOL
  *	value:          0
  *	index:          0
  *	data            version number (16 bits little endian)
+ *                     1 for original accessory support
+ *                     2 adds HID and device to host audio support
  */
 #define ACCESSORY_GET_PROTOCOL  51
 
@@ -70,6 +72,65 @@
  */
 #define ACCESSORY_START         53
 
+/* Control request for registering a HID device.
+ * Upon registering, a unique ID is sent by the accessory in the
+ * value parameter. This ID will be used for future commands for
+ * the device
+ *
+ *	requestType:    USB_DIR_OUT | USB_TYPE_VENDOR
+ *	request:        ACCESSORY_REGISTER_HID_DEVICE
+ *	value:          Accessory assigned ID for the HID device
+ *	index:          total length of the HID report descriptor
+ *	data            none
+ */
+#define ACCESSORY_REGISTER_HID         54
+
+/* Control request for unregistering a HID device.
+ *
+ *	requestType:    USB_DIR_OUT | USB_TYPE_VENDOR
+ *	request:        ACCESSORY_REGISTER_HID
+ *	value:          Accessory assigned ID for the HID device
+ *	index:          0
+ *	data            none
+ */
+#define ACCESSORY_UNREGISTER_HID         55
+
+/* Control request for sending the HID report descriptor.
+ * If the HID descriptor is longer than the endpoint zero max packet size,
+ * the descriptor will be sent in multiple ACCESSORY_SET_HID_REPORT_DESC
+ * commands. The data for the descriptor must be sent sequentially
+ * if multiple packets are needed.
+ *
+ *	requestType:    USB_DIR_OUT | USB_TYPE_VENDOR
+ *	request:        ACCESSORY_SET_HID_REPORT_DESC
+ *	value:          Accessory assigned ID for the HID device
+ *	index:          offset of data in descriptor
+ *                      (needed when HID descriptor is too big for one packet)
+ *	data            the HID report descriptor
+ */
+#define ACCESSORY_SET_HID_REPORT_DESC         56
+
+/* Control request for sending HID events.
+ *
+ *	requestType:    USB_DIR_OUT | USB_TYPE_VENDOR
+ *	request:        ACCESSORY_SEND_HID_EVENT
+ *	value:          Accessory assigned ID for the HID device
+ *	index:          0
+ *	data            the HID report for the event
+ */
+#define ACCESSORY_SEND_HID_EVENT         57
+
+/* Control request for setting the audio mode.
+ *
+ *	requestType:	USB_DIR_OUT | USB_TYPE_VENDOR
+ *	request:        ACCESSORY_SET_AUDIO_MODE
+ *	value:          0 - no audio
+ *                     1 - device to host, 44100 16-bit stereo PCM
+ *	index:          0
+ *	data            none
+ */
+#define ACCESSORY_SET_AUDIO_MODE         58
+
 /* ioctls for retrieving strings set by the host */
 #define ACCESSORY_GET_STRING_MANUFACTURER   _IOW('M', 1, char[256])
 #define ACCESSORY_GET_STRING_MODEL          _IOW('M', 2, char[256])
@@ -79,5 +140,7 @@
 #define ACCESSORY_GET_STRING_SERIAL         _IOW('M', 6, char[256])
 /* returns 1 if there is a start request pending */
 #define ACCESSORY_IS_START_REQUESTED        _IO('M', 7)
+/* returns audio mode (set via the ACCESSORY_SET_AUDIO_MODE control request) */
+#define ACCESSORY_GET_AUDIO_MODE            _IO('M', 8)
 
 #endif /* __LINUX_USB_F_ACCESSORY_H */
diff --git a/include/linux/usb/usbnet.h b/include/linux/usb/usbnet.h
index 6939637e787d..b262fd7caa6e 100644
--- a/include/linux/usb/usbnet.h
+++ b/include/linux/usb/usbnet.h
@@ -192,7 +192,8 @@ extern void usbnet_cdc_status(struct usbnet *, struct urb *);
 enum skb_state {
 	illegal = 0,
 	tx_start, tx_done,
-	rx_start, rx_done, rx_cleanup
+	rx_start, rx_done, rx_cleanup,
+	unlink_start
 };
 
 struct skb_data {	/* skb->cb is one of these */
diff --git a/include/media/nvc_focus.h b/include/media/nvc_focus.h
index e37d897d8323..2c60db318da2 100644
--- a/include/media/nvc_focus.h
+++ b/include/media/nvc_focus.h
@@ -35,6 +35,14 @@
 
 #define AF_POS_INVALID_VALUE INT_MAX
 
+/* These are the slew rate values coming down from the configuration */
+/* Disabled is the same as fastest. Default is the default */
+/* slew rate configuration in the focuser */
+#define SLEW_RATE_DISABLED		0
+#define SLEW_RATE_DEFAULT		1
+#define SLEW_RATE_SLOWEST		9
+
+
 enum nvc_focus_sts {
 	NVC_FOCUS_STS_UNKNOWN		= 1,
 	NVC_FOCUS_STS_NO_DEVICE,
diff --git a/include/media/ov9726.h b/include/media/ov9726.h
index b1e759ba583c..fb9995b4a8de 100644
--- a/include/media/ov9726.h
+++ b/include/media/ov9726.h
@@ -19,7 +19,8 @@
 #define OV9726_IOCTL_SET_FRAME_LENGTH	_IOW('o', 2, __u32)
 #define OV9726_IOCTL_SET_COARSE_TIME	_IOW('o', 3, __u32)
 #define OV9726_IOCTL_SET_GAIN		_IOW('o', 4, __u16)
-#define OV9726_IOCTL_GET_STATUS		_IOR('o', 5, __u8)
+#define OV9726_IOCTL_GET_STATUS	_IOR('o', 5, __u8)
+#define OV9726_IOCTL_SET_GROUP_HOLD	_IOW('o', 6, struct ov9726_ae)
 
 struct ov9726_mode {
 	int	mode_id;
@@ -30,6 +31,15 @@ struct ov9726_mode {
 	__u16	gain;
 };
 
+struct ov9726_ae {
+	__u32 frame_length;
+	__u32 coarse_time;
+	__u16 gain;
+	__u8 frame_length_enable;
+	__u8 coarse_time_enable;
+	__u8 gain_enable;
+};
+
 struct ov9726_reg {
 	__u16	addr;
 	__u16	val;
diff --git a/include/media/tegra_camera.h b/include/media/tegra_camera.h
index 9dea1485781d..3c41864cc71f 100644
--- a/include/media/tegra_camera.h
+++ b/include/media/tegra_camera.h
@@ -2,6 +2,7 @@
  * include/linux/tegra_camera.h
  *
  * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012, NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -48,6 +49,15 @@ enum StereoCameraMode {
 	StereoCameraMode_Force32 = 0x7FFFFFFF
 };
 
+struct tegra_camera_platform_data {
+	bool limit_3d_emc_clk;
+};
+
+#if  defined(CONFIG_TEGRA_CAMERA)
+int is_tegra_camera_on(void);
+#else
+int is_tegra_camera_on(void) { return 0; }
+#endif
 
 #define TEGRA_CAMERA_IOCTL_ENABLE		_IOWR('i', 1, uint)
 #define TEGRA_CAMERA_IOCTL_DISABLE		_IOWR('i', 2, uint)
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index e0583b7769cb..3bfd6e58b60c 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -408,6 +408,11 @@ enum snd_soc_dapm_type {
 	snd_soc_dapm_aif_out,		/* audio interface output */
 };
 
+enum snd_soc_dapm_subclass {
+	SND_SOC_DAPM_CLASS_INIT	= 0,
+	SND_SOC_DAPM_CLASS_PCM	= 1,
+};
+
 /*
  * DAPM audio route definition.
  *
diff --git a/include/sound/soc.h b/include/sound/soc.h
index aa19f5a32ba8..878807c0c283 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -751,6 +751,7 @@ struct snd_soc_card {
 
 	struct list_head list;
 	struct mutex mutex;
+	struct mutex dapm_mutex;
 
 	bool instantiated;
 
diff --git a/include/trace/events/nvevent.h b/include/trace/events/nvevent.h
new file mode 100644
index 000000000000..30987129deaf
--- /dev/null
+++ b/include/trace/events/nvevent.h
@@ -0,0 +1,100 @@
+/*
+ * include/trace/events/nvevent.h
+ *
+ * Input event logging to ftrace.
+ *
+ * Copyright (c) 2012, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM nvevent
+
+#if !defined(_TRACE_NVEVENT_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_NVEVENT_H
+
+#include <linux/ktime.h>
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(nvevent_irq_data_read_start_series,
+	TP_PROTO(const char *name),
+	TP_ARGS(name),
+	TP_STRUCT__entry(
+		__field(const char *, name)
+	),
+	TP_fast_assign(
+		__entry->name = name;
+	),
+	TP_printk("name=%s",
+	  __entry->name)
+);
+
+TRACE_EVENT(nvevent_irq_data_read_finish_series,
+	TP_PROTO(const char *name),
+	TP_ARGS(name),
+	TP_STRUCT__entry(
+		__field(const char *, name)
+	),
+	TP_fast_assign(
+		__entry->name = name;
+	),
+	TP_printk("name=%s",
+	  __entry->name)
+);
+
+TRACE_EVENT(nvevent_irq_data_read_start_single,
+	TP_PROTO(const char *name),
+	TP_ARGS(name),
+	TP_STRUCT__entry(
+		__field(const char *, name)
+	),
+	TP_fast_assign(
+		__entry->name = name;
+	),
+	TP_printk("name=%s",
+	  __entry->name)
+);
+
+TRACE_EVENT(nvevent_irq_data_read_finish_single,
+	TP_PROTO(const char *name),
+	TP_ARGS(name),
+	TP_STRUCT__entry(
+		__field(const char *, name)
+	),
+	TP_fast_assign(
+		__entry->name = name;
+	),
+	TP_printk("name=%s",
+	  __entry->name)
+);
+
+TRACE_EVENT(nvevent_irq_data_submit,
+	TP_PROTO(const char *name),
+	TP_ARGS(name),
+	TP_STRUCT__entry(
+		__field(const char *, name)
+	),
+	TP_fast_assign(
+		__entry->name = name;
+	),
+	TP_printk("name=%s",
+	  __entry->name)
+);
+
+#endif /*  _TRACE_NVEVENT_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/include/trace/events/power.h b/include/trace/events/power.h
index 5b503e9b661c..a6be189a2b5f 100644
--- a/include/trace/events/power.h
+++ b/include/trace/events/power.h
@@ -306,6 +306,20 @@ DEFINE_EVENT(clock, clock_set_rate,
 	TP_ARGS(name, state, cpu_id)
 );
 
+DEFINE_EVENT(clock, clock_lock,
+
+	TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
+
+	TP_ARGS(name, state, cpu_id)
+);
+
+DEFINE_EVENT(clock, clock_unlock,
+
+	TP_PROTO(const char *name, unsigned int state, unsigned int cpu_id),
+
+	TP_ARGS(name, state, cpu_id)
+);
+
 /*
  * The power domain events are used for power domains transitions
  */
diff --git a/include/trace/events/workqueue.h b/include/trace/events/workqueue.h
index 7d497291c85d..82f61f4ce7a7 100644
--- a/include/trace/events/workqueue.h
+++ b/include/trace/events/workqueue.h
@@ -54,7 +54,7 @@ TRACE_EVENT(workqueue_queue_work,
 		__entry->function	= work->func;
 		__entry->workqueue	= cwq->wq;
 		__entry->req_cpu	= req_cpu;
-		__entry->cpu		= cwq->gcwq->cpu;
+		__entry->cpu		= cwq->pool->gcwq->cpu;
 	),
 
 	TP_printk("work struct=%p function=%pf workqueue=%p req_cpu=%u cpu=%u",